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P520-19SC 参数 Datasheet PDF下载

P520-19SC图片预览
型号: P520-19SC
PDF下载: 下载PDF文件 查看货源
内容描述: 低相位噪声压控与乘数(为65-130MHz基金XTAL) [Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)]
分类和应用: 石英晶振压控振荡器
文件页数/大小: 7 页 / 240 K
品牌: PLL [ PHASELINK CORPORATION ]
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PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
FEATURES
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 800MHz (selectable 1x,
2x, 4x and 8x multipliers).
Low Injection Power for crystal 50uW.
Available outputs: PECL, LVDS, or CMOS.
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in 16 pin (TSSOP or SOIC)
PIN CONFIGURATION
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
PLL 520-1x
DESCRIPTION
The PLL520-17/-18/-19 family of VCXO IC’s is
specifically designed to pull high frequency
fundamental crystals. They achieve very low current
into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency
pulling, controlled by the VCON input.
^: Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-18
PLL520-17
PLL520-19
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
BLOCK DIAGRAM
OE input: Logical states defined by PECL levels for PLL520-18
Logical states defined by CMOS levels for PLL520-17/-19
SEL
OE
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
Q
Q
PLL by-pass
PLL520-17/-18/-19
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1