Preliminary
P521-28
Low Phase Noise PECL VCXO (100MHz to 200MHz)
FEATURES
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100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100MHz – 200MHz.
Complementary PECL outputs.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
High pull linearity: < 5%.
+/- 125 ppm pull range
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DIE CONFIGURATION
57.5 mil
VDDOSC
OSCOFF
OESEL
V
N/C
N/C
(1460,1435)
GNDOSC
VCON
XIN
18
17
16
15
14
13
12
VDDANA
VDDBUF
VDDBUF
PECLBAR
PECL
GNDBUF
19
11
20
10
9
8
56.5 mil
XOUT
OE
21
7
22
1
2
3
4
5
6
GNDOSC
GNDANA
GNDANA
VCON
GNDBUF
Y
(0,0)
DESCRIPTIONS
P521-28 is a VCXO IC specifically designed to pull
high frequency fundamental crystals. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input. The chip provides a
low phase noise, low jitter PECL differential clock
output.
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
56.5 x 57.5 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
OE
VCON
Oscillator
X+
X-
Q
Q
OUTPUT ENABLE LOGIC SELECTION
OESEL
(Pad #14)
0 (Default)
OECTRL
(Pad #22)
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
Amplifier
w/
integrated
varicaps
P521-28
1
Pad #14, 22: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #22: Logical states defined by PECL V
I H
and V
I L
levels.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
GNDBUF
Rev 3/02/04 Page 1
PLL [ PHASELINK CORPORATION ]
