Preliminary
PLL600-27F
Low Power 5 Output XO 10MHz to 52MHz
FEATURES
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Generates 5 CMOS outputs.
10 to 52MHz fundamental or 3
rd
OT crystal input.
Low phase noise (-130 dBc @ 10kHz offset).
Low jitter (RMS): 2.5ps period jitter.
12mA drive capability at TTL output.
1.62V to 3.63V DC operation.
Available in 14 pin 150mil SOIC.
PIN ASSIGNMENT
XIN/FIN
GND
CLK1
GND
1
2
14
13
XOUT
GND
CLK5
VDD
CLK4
VDD
CLK3
PLL600-27F
3
4
5
6
7
12
11
10
9
8
DESCRIPTION
The PLL600-27F is part of PhaseLink’s low cost
family of XO IC’s, designed to replace multiple XO
solutions saving the cost and board space of clock
distribution buffers. In addition, it provides among
the lowest current on the market for the 10MHz to
52MHz range. It accepts input crystals from 10 to
52MHz (fundamental resonant mode) and provides
low phase noise (<-130dBc at 10kHz offset at
30MHz), and very low jitter (2.5 ps RMS period jitter)
outputs.
CLK2
GND
N/C
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
CLK1
CLK2
CLK3
CLK4
CLK5
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 1
PLL [ PHASELINK CORPORATION ]
