Analog Frequency Multiplier
PL560-xx VCXO Family
ꢀ
L 2 X
V C O N
O E
X IN
Q B A R
Q
F re q u e n c y
X 2
F re q u e n c y
X 4
O s c illa to rꢀ
A m p lifie rꢀ
X O U T
O n ly ꢀre q u ire d ꢀin ꢀx 4 ꢀd e s ig n s
L 4 X
ꢀ
Figure 2: Block Diagram of VCXO AFM
ꢀ
Figureꢀ3ꢀshowsꢀtheꢀperiodꢀjitterꢀhistogramꢀofꢀtheꢀ2xꢀAnalogꢀFrequencyꢀMultiplierꢀatꢀ311.04ꢀMHz,ꢀwhileꢀFigureꢀ4ꢀshowsꢀtheꢀveryꢀ
lowꢀrejectionꢀlevelsꢀofꢀsubꢁharmonicsꢀthatꢀcorrespondꢀtoꢀtheꢀexceptionallyꢀlowꢀjitterꢀperformance.ꢀ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
Figure 3: Period Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonics below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
OE
Output State
0ꢀ(Default)ꢀ
Enabledꢀ
Triꢁstateꢀ
Triꢁstateꢀ
Enabledꢀ
Triꢁstateꢀ
Enabledꢀ
Enabledꢀ
Triꢁstateꢀ
0ꢀ(Default)ꢀ
1ꢀ
PECLꢀ
0ꢀ
1ꢀ
0ꢀ(Default)ꢀ
1ꢀ
1ꢀ(Default)ꢀ
0ꢀ
1ꢀ(Default)ꢀ
0ꢀ(Default)ꢀ
1ꢀ
LVDSꢀorꢀCMOSꢀ
OESELꢀandꢀOE:ꢀConnectꢀtoꢀVDDꢀtoꢀsetꢀtoꢀ“1”,ꢀconnectꢀtoꢀGNDꢀtoꢀsetꢀtoꢀ“0”.ꢀInternallyꢀsetꢀtoꢀdefaultꢀthroughꢀpullꢁdownꢀ/ꢀꢁup.
47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ2ꢀꢀ
PLL [ PHASELINK CORPORATION ]
