Analog Frequency Multiplier
PL560-xx VCXO Family
ꢀ
Figure 5: Diagram Representation of the Related System Inductance and Capacitance
DIE SIDE
ꢁꢀCinternalꢀ=ꢀBasedꢀonꢀAFMꢀdeviceꢀ
ꢁꢀCpadꢀ=ꢀ2.0ꢀpF,ꢀBondꢀpadꢀandꢀitsꢀESDꢀcircuitryꢀꢀ
ꢁꢀC11ꢀ=ꢀ0.4ꢀpF,ꢀTheꢀfollowingꢀamplifierꢀstageꢀ
PCB side
ꢀ
ꢀ
ꢁꢀLWB1ꢀ=ꢀ2ꢀnH,ꢀ(2ꢀplaces),ꢀStrayꢀinductanceꢀ
ꢁꢀCstrayꢀ=ꢀ1.0ꢀpF,ꢀStrayꢀcapacitanceꢀ
ꢁꢀL2Xꢀ(L4X)ꢀ=ꢀ2xꢀorꢀ4xꢀinductorꢀ
ꢁꢀC2Xꢀ(C4X)ꢀ=ꢀrangeꢀ(0.1ꢀtoꢀ2.7ꢀpF),ꢀFineꢀtuneꢀꢀꢀꢀ
ꢀꢀinductorꢀifꢀusedꢀ
ꢀ
•ꢀThereꢀareꢀtwoꢀdefaultꢀvariablesꢀthatꢀnormallyꢀwillꢀnotꢀneedꢀtoꢀbeꢀmodified.ꢀꢀTheseꢀareꢀCpad,ꢀandꢀC11ꢀandꢀ
areꢀfoundꢀinꢀcellsꢀB22ꢀandꢀB27ꢀofꢀ‘AFMꢀTuningꢀAssistant’,ꢀrespectively.ꢀ
•ꢀLWB1ꢀisꢀtheꢀcombinedꢀstrayꢀinductanceꢀinꢀtheꢀlayout.ꢀꢀTheꢀDIEꢀwireꢀbondꢀisꢀ~ꢀ0.6ꢀnHꢀandꢀinꢀtheꢀcaseꢀofꢀaꢀ
leadedꢀpartꢀanꢀadditionalꢀ1.0ꢀnHꢀisꢀadded.ꢀꢀYourꢀlayoutꢀinductanceꢀmustꢀbeꢀaddedꢀtoꢀthese.ꢀꢀThereꢀareꢀ2ꢀofꢀ
theseꢀandꢀtheyꢀareꢀassumedꢀtoꢀbeꢀapproximatelyꢀsymmetricalꢀsoꢀyouꢀonlyꢀneedꢀtoꢀenterꢀthisꢀinductanceꢀ
onceꢀinꢀcellꢀB23.ꢀ
•ꢀEnterꢀtheꢀstrayꢀparasiticꢀcapacitanceꢀintoꢀcellꢀB26.ꢀꢀAnꢀadditionalꢀ0.5ꢀpFꢀmustꢀbeꢀaddedꢀtoꢀthisꢀvalueꢀifꢀaꢀ
leadedꢀpartꢀisꢀused.ꢀ
•ꢀEnterꢀtheꢀappropriateꢀvalueꢀforꢀCinternalꢀintoꢀB21ꢀbasedꢀonꢀtheꢀdeviceꢀusedꢀ(seeꢀcolumnꢀD).ꢀꢀUseꢀtheꢀ‘AFMꢀ
TuningꢀAssistant’ꢀsoftwareꢀtoꢀcalculateꢀL2Xꢀ(andꢀC2Xꢀifꢀused)ꢀforꢀyourꢀresonanceꢀfrequency.ꢀ
•ꢀForꢀ4XꢀAFMs,ꢀrepeatꢀtheꢀsameꢀprocedureꢀinꢀtheꢀL4Xꢀworksheet.ꢀ
•ꢀSeeꢀtheꢀexamplesꢀinꢀtheꢀfollowingꢀsection.ꢀ
47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ6ꢀꢀ
PLL [ PHASELINK CORPORATION ]
