Analog Frequency Multiplier
PL560-xx VCXO Family
VCON
L2X
OE
X IN
O s c illa to r
A m p lifie r
F re q u e n c y
X2
F re q u e n c y
X4
QBAR
Q
XOUT
O n ly r e q u ir e d in x 4 d e s ig n s
L4X
Figure 2: Block Diagram of VCXO AFM
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 311.04 MHz, while Figure 4 shows the very
low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Period Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonics below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
0 (Default)
PECL
1
OE
0 (Default)
1
0
1 (Default)
0
1 (Default)
0 (Default)
1
Output State
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
0 (Default)
LVDS or CMOS
1
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
Rev.:02-09-07 Page 2
PLL [ PHASELINK CORPORATION ]
