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PL56068OI 参数 Datasheet PDF下载

PL56068OI图片预览
型号: PL56068OI
PDF下载: 下载PDF文件 查看货源
内容描述: 模拟倍频器 [Analog Frequency Multiplier]
分类和应用: 倍频器
文件页数/大小: 15 页 / 500 K
品牌: PLL [ PHASELINK CORPORATION ]
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Analog Frequency Multiplier
VCXO Family of Products
PACKAGE PIN DESCRIPTION AND ASSIGNMENT
GNDBUF
OSCOFFSEL
GNDOSC
VCON
XIN
XOUT
OECTRL
DNC
GNDANA
1
2
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
L2X
VDDOSC
OESEL
VDDANA
VDDBUF
QBAR
Q
OSCOFFSEL
GNDOSC
1
2
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
L2X
VDDOSC
OESEL
VDDANA
VDDBUF
QBAR
Q
3
4
5
6
7
8
VDDANA
OESEL
VDDOSC
L2X
13
14
15
16
12
11
10
9
8
7
6
5
GNDANA
DNC
OECTRL
XOUT
VCON
XIN
XOUT
OECTRL
L4X
3
4
5
6
7
8
VDDANA
OESEL
VDDOSC
L2X
13
14
15
16
12
11
10
GNDBUF
9
VDDBUF
VDDBUF
QBAR
QBAR
Q
Q
OSCOFF
SEL
GNDOSC
OSCOFF
SEL
GNDOSC
XIN
GNDBUF
VCON
VDDOSC
GNDBUF
2X AFM Package Pin Out
4X AFM Package Pin Out
PIN ASSIGNMENTS
Name
OSCOFFSEL
GNDOSC
VCON
XIN
XOUT
OECTRL
DNC
L4X
7
I
Pin#
1
2
3
4
5
6
Type
I
P
I
I
O
I
Product
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X
4X
Description
Set to “0” (GND) to choose to turn off the oscillator when outputs are disabled (OE). Default (no
connect) is OSC always on.
GND connection for oscillator circuitry.
Control Voltage input. Use this pin to change the output frequency by varying the applied Control
Voltage.
Input from crystal oscillator circuitry.
Output from crystal oscillator circuitry.
Output Enable input (see "OE LOGIC SELECTION TABLE").
Do Not Connect.
External inductor connection. The inductor is recommended to be a high Q small
size 0402 or 0603 SMD component, and must be placed between L4X and adjacent
VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects
and to maintain inductor Q. This inductor is used with 4X AFMs.
GND connection.
VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other
VDDs whenever possible.
GND connection for output buffer circuitry.
PECL/LVDS or CMOS output.
Complementary PECL/LVDS output or in phase CMOS.
VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other
VDDs whenever possible.
VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs
whenever possible.
Selector input to choose the OE control logic (see “OE SELECTION TABLE”.
VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other
VDDs whenever possible.
External inductor connection. The inductor is recommended to be a high Q small
size 0402 or 0603 SMD component, and must be placed between L2X and adjacent
VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects
and to maintain inductor Q.
GNDANA
8
VDDOSC
GNDBUF
Q
QBAR
VDDBUF
VDDANA
OESEL
VDDOSC
L2X
9
10
11
12
13
14
15
16
P
O
O
P
P
I
P
I
P
2X
4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:03-22-05 Page 13
VCON
XIN
PLL560-4X
PLL560-0X
8
7
6
5
VDDOSC
L4X
OECTRL
XOUT
P560-4X
1
2
3
4
P560-0X
1
2
3
4