Analog Frequency Multiplier
VCXO Family of Products
L 2 X
V C o n
O E C T R L
X IN
Q B A R
Q
F re q u e n cy
X 2
F re q u e n cy
X 4
O scilla to r
A m p lifie r
X O U T
O n ly re q u ire d in x4 d e sig n s
L 4 X
Figure 2: Overall VCXO AFM Block Diagram
Figure 3 shows the jitter histogram of the 2x Analog Frequency Multiplier at 155.52MHz, while figure 4 shows the very low
rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonic below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
OE
Output State
0 (Default)
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
0 (Default)
1
PECL
0
1
0 (Default)
1
1 (Default)
0
1 (Default)
0 (Default)
1
LVDS or CMOS
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 2
PLL [ PHASELINK CORPORATION ]
