(Preliminary)
PL610-01
1.8V to 3.3V, 1MHz to 130MHz XO IC
KEY PROGRAMMING PARAMETERS (Optional)
CLK[0:1]
Output Frequency
F
OUT
= F
REF
/ P*
(*: P is an Odd/Even Divider)
Where P = 6 bit
CLK0 = F
REF
, F
REF
/2 or F
REF
/ P
CLK1 = F
REF
, F
REF
/2 or CLK0
Output Drive Strength
Three optional drive strengths
to choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
OE - input
PDB - input
CLK1 – output
PACKAGE PIN AND DIE PAD ASSIGNMENT
Name
XIN, FIN
Pin Assignment
DFN-6L
1
SOT23-6L
3
Type
I
Description
Crystal or Reference Clock input pin
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB) input or CLK1
clock output. This pin has an internal 60KΩ
pull up resistor
for OE and 10MΩ
pull
up resistor for PDB.
2
1
I/O
State
0
1 (default)
GND
CLK0
VDD
XOUT
3
4
5
6
2
6
5
4
P
O
P
O
GND connection
Programmable Clock Output
VDD connection
Crystal Output pin
Do Not Connect (DNC ) when FIN is present
OE
Tri-state CLK
Normal mode
PDB
Power Down Mode
Normal mode
OE, PDB,
CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 4/2/07 Page 2
PLL [ PHASELINK CORPORATION ]
