PL611-20
Programmable Quick Turn Clock
T M
DIE SPECIFICATION
Name
Size
Reverse side
Pad Opening
Die Thickness
Value
31.5x55.1 mil
GND
80 micron x 80 micron
10 mil
PAD LAYOUT AND DIE ID
XIN
GND
GND
CLK0
CLK1
1
2
3
7
4
5
6
VDD
VDD
9
8
XOUT
CLK2, OE, FSEL
Note: CLK0=CLK1
PAD ASSIGNMENT and DESCRIPTION
Name
XIN
GND
CLK0
CLK1
VDD
VDD
Pad #
1
2
3
4
5
6
7
Die Pads
X (µm)
101.5
101.5
101.5
101.5
101.5
697
697
Y(µm)
1274.0
1075.0
878.4
671.8
425.0
483.0
790.0
Type
I
P
O
O
P
Crystal input.
GND connection.
Description
Optional same frequency clock output (CLK0=CLK1). If the
clock output is not used, the pad should remain as ‘Do Not
Connect (DNC).
Programmable Clock Output.
VDD connection.
This programmable I/O pin can be configured as CLK2
(FIN
or FIN/2)
output, or OE input, or Frequency
Selection (FSEL) input pin. This pin has an internal
60KΩ pull up resistor.
State
0
1 (default)
OE
Tristate
CLK[0:1]
Normal
mode
FSEL
Select Freq. ‘1’
Select Freq. ‘2’
CLK2, OE, FSEL
8
697
1024.0
O
XOUT
9
697
1274.0
O
Crystal output.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
Rev 07/06/05 Page 3
PLL [ PHASELINK CORPORATION ]
