PL611-20
Programmable Quick Turn Clock
T M
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ]
Output Frequency
Fout = FIN * M / (R * P) where
M=10 bit
R = 8 bit
P = 5 bit
1. CLK[0:1] = VCO / 2 * P
2. CLK0 = ~ CLK1
2. CLK[2]= FIN or FIN/2
Output Drive
Strength
Std: 10mA
(default)
High: 24mA
Crystal Load
+/- 200ppm
tuning.
Programmable
Input/Output (pin #7)
One output pin can be
configured as
1. CLK2 = FIN or FIN/2
2. FSEL - input
3. OE - input
Charge-Pump
Current
4 levels of pump
current setting
PIN DESCRIPTION
Name
XIN/FIN
GND
CLK[0:1]
VDD
DNC
Pin #
(M)SOP-8
1
2
3,4
5
6
SOT-23
3
2
1
6
-
Type
I
P
O
P
-
Description
Crystal or Reference input pin
GND connection
Programmable Clock Output [note:CLK0=CLK1]
VDD connection (2.25~3.63V)
Do No Connect
This programmable I/O pin can be configured as CLK2
(FIN
or FIN/2)
output, or OE input, or Frequency
Selection (FSEL) input pin. This pin has an internal 60KΩ
pull up resistor.
State
0
1 (default)
OE
Tristate
CLK[0:1]
Normal
mode
FSEL
Select Freq. ‘1’
Select Freq. ‘2’
CLK2, OE, FSEL
7
5
B
XOUT
8
4
O
Crystal output pin
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
Rev 07/06/05 Page 2
PLL [ PHASELINK CORPORATION ]
