(Preliminary)
PL611s-06
Low-Power Programmable Quick Turn Clock
T M
FUNCTIONAL DESCRIPTION
PL611s-06 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-06 accepts a fundamental crystal input of 10MHz to 30MHz or
reference clock input of 1MHz to 100MHz and is capable of producing two outputs up to 35MHz. This flexible
design allows the PL611s-06 to deliver any PLL generated frequency, F
REF
(Crystal or Ref Clk) frequency or
F
REF
/2 to CLK0 and/or CLK1. Some of the design features of the PL611s-06 are mentioned below:
PLL Programming
The PLL in the PL611s-06 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of the
PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by the
following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (F
VCO
/(2*P)),
F
REF
(Crystal or Ref Clk Frequency) output, or F
REF
/2
output. The output drive level can be programmed to
Low Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is 35MHz.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up resistor
giving a default condition of logic “1”.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-06 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference ( Crystal or Ref Clk ) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 3
PLL [ PHASELINK CORPORATION ]
