(Preliminary)
PL611s-16
1.8V-3.3V PicoPLL
TM
32K Programmable Clock
PACKAGE PIN ASSIGNMENT
Name
VDD
GNDA
FIN
LF
GND
CLK0
SOT
1
2
3
4
5
6
Pin #
SC70
3
2
1
6
5
4
DFN
3
2
1
6
5
4
Type
P
P
I
I
P
O
VDD connection.
Description
Ground connection for Analog Circuitry.
Reference input pin.
Loop Filter input pin.
GND connection
Programmable Clock Output
GUIDELINES FOR EXTERNAL COMPONENT SELECTION
For the optimum performance, accurate external loop filter components must be selected. A general guideline for
selecting these components based on the input frequency is shown in the below table. Please contact PhaseLink
for more accurate component selections.
Input frequency
3MHz ~ 200MHz
300KHz ~ 10MHz
30KHz ~ 1.0MHz
10KHz ~ 100KHz
Capacitor Value
4.7nF
4.7nF
4.7nF
47nF
Resistor Value
2.2KΩ
6.8KΩ
22KΩ
22KΩ
APPLICATION RECOMMENDATIONS FOR PL611s-16
PL611s-16 can accept a reference input >10KHz and produce a clock output in the MHz range, as shown in the
diagram ‘1’, below. However, to save costs in consumer product system designs and for greater area optimization,
it is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-16, as shown
in diagram ‘2’, below.
XIN
REFIN
C1
LF
LPGND
MHZ CLK
(Any Frequency
PL611s-
15
XIN
32.768K
Hz
ASIC
C2
XOUT
XOUT
1.8~3.3V
REFIN
LF
LPGND
MHZ CLK
(Any Frequency)
PL611s-
15
1.8~3.3V
Diagram ‘1’
Note: An AC Coupling Cap may be required if RTC Clock amplitude is too small.
Diagram ‘2’
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/06 Page 2
PLL [ PHASELINK CORPORATION ]
