(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
FEATURES
•
Advanced Programmable PLL design for low-
frequency (kHz) input applications.
•
Input Frequency: 10kHz to 200MHz
•
OTP selectable AC/DC Input Coupling.
•
Accepts >0.1V reference signal input voltage
•
Very low Jitter and Phase Noise
•
Output Frequency:
o
<65MHz @ 1.8V operation
o
<90MHz @ 2.5V operation
o
<125MHz @ 3.3V operation
•
Disabled outputs programmable as HiZ or Active Low.
•
Offered in Tiny
GREEN/RoHS
compliant packages
o
6-pin DFN (2.0mmx1.3mmx0.6mm)
o
6-pin SC70 (2.3mmx2.25mmx1.0mm)
o
6-pin SOT23 (3.0mmx3.0mmx1.35mm)
•
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
•
Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-17 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLL
TM
Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance, low
power applications, the PL611s-17 accepts a low
frequency (>10KHz) Reference input and generates
up to 125MHz outputs with the best phase noise,
jitter performance, and power consumption for
handheld devices and notebook applications. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(F
OUT
, F
REF
, F
REF
/2) output. Cascading the PL611s-
17 with other PicoPLL ICs can result in producing all
required system clocks with specific savings in board
space, power consumption, and cost.
PACKAGE PIN CONFIGURATION
OE, PDB,
FSEL, CLK1
VDD
FIN
LF
1
2
3
6
5
4
CLK0
GND
GND
CLK0
LF
SOT23-
SOT23-6L
23
mmx3 mmx1 35mm
mm)
(3.0mmx3.0mmx1.35mm)
3
2
PL611s-17
PL611s-17
PL611s-17
PL611s-17
1
6
5
4
FIN
OE, PDB,
FSEL, CLK1
VDD
PL611s-17
FIN
OE, PDB, FSEL, CLK1
VDD
1
2
3
6
5
4
LF
GND
CLK0
DFN-
DFN-6L
mmx1 mmx0 mm)
(2.0mmx1.3mmx0.6mm)
BLOCK DIAGRAM
Ref.
R-Counter
(7-bit)
M-Counter
(16-bit)
PL611s-17
SC70-
SC70-6L
70
mmx2 25mmx mm)
mmx1
(2.3mmx2.25mmx1.0mm)
FIN
Phase
Detector
Charge
Pump
F
VCO
= F
Ref
* (M/R)
VCO
Programmable
Function
F
Out
= F
VCO
P-Counter
(4-bit)
/2*P
CLK0
Programming
Logic
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 1
PLL [ PHASELINK CORPORATION ]
