(Preliminary)
PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock
TM
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 8 bit
R = 5 bit
P = 14 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
•
•
•
•
OE - input
FSEL - input
PDB – input
HiZ or Active Low disabled state
PIN CONFIGURATION AND DESCRIPTION
CLK1
FIN
CLK1
GND
1
2
3
6
5
4
OE, PDB, FSEL
VDD
OE, PDB, FSEL
CLK0
CLK1
1
2
3
6
5
4
CLK0
VDD
OE, PDB, FSEL
PL611s-19
1
2
3
6
5
4
CLK0
GND
GND
FIN
VDD
DFN-
DFN-6L
mmx1 mmx0 mm)
(2.0mmx1.3mmx0.6mm)
PL611s-19
PL611s-19
PL611s-19
PL611s-19
PL611s-19
PL611s-19
PL611s-19
FIN
SC70-
SC70-6L
70
mmx2 25mmx mm)
mmx1
(2.3mmx2.25mmx1.0mm)
SOT23-
SOT23-6L
23
mmx3 mmx1 35mm
mm)
(3.0mmx3.0mmx1.35mm)
Name
CLK1
GND
FIN
Pin Assignment
DFN
SC70
SOT
Pin#
Pin#
Pin #
2
3
1
1
5
3
1
2
3
Type
I/O
P
I
Programmable Clock Output
GND connection
Reference input pin
Description
OE, PDB,
FSEL
6
2
4
O
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or On-the-Fly Frequency Switching
Selector (FSEL). This pin has an internal 60K pull up resistor for OE,
PDB & FSEL.
The OE and PDB features can be programmed to allow the output to float
(Hi Z), or to operate in the ‘Active low’ mode.
VDD
CLK0
5
4
4
6
5
6
P
O
VDD connection
Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE
1
0
N/A
N/A
PDB
N/A
N/A
1
0
Osc.
On
On
On
Off
PLL
On
Off
On
Off
CLK0
On
HiZ or Active Low
On
HiZ or Active Low
CLK1
On
On
On
HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
PLL [ PHASELINK CORPORATION ]
