(Preliminary)
PL611s-26
1.8V-3.3V PicoPLL
TM
Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
OE - input
•
PDB - input
•
CLK1 – output
PACKAGE PIN CONFIGURATION AND DESCRIPTION
OE, PDB, CLK1
FIN
OE,PDB,CLK1
GND
1
2
3
6
5
4
FSEL
VDD
CLK0
GND
FIN
1
2
3
6
5
4
CLK0
VDD
FSEL
PL611s-26
PL611s-26
PL611s-26
PL611s-26
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
mmx1 mmx0 mm)
SOT23-
SOT23-6L
23
(3.0mmx3.0mmx1.35mm)
mmx3 mmx1 35mm)
mm
PIN DESCRIPTION
Name
Pin Assignment
DFN Pin# SOT Pin #
Type
Description
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or CLK1 Clock output. This pin has an
internal 60K pull up resistor (OE and PDB functions only).
2
1
I/O
Pin State
0
1 (default)
GND
FIN
3
1
2
3
P
I
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
OE,
PDB,
CLK1
FSEL
6
4
I
GND connection
Reference input pin
Frequency Switching Input pin. This pin has an internal 60K
resistor.
FSEL
State
0
1 (default)
Frequency 2
Frequency 1
pull up
VDD
CLK0
5
4
5
6
P
O
VDD connection
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
PLL [ PHASELINK CORPORATION ]
