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PL611S-28-XXXGI 参数 Datasheet PDF下载

PL611S-28-XXXGI图片预览
型号: PL611S-28-XXXGI
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V - 3.3V PicoPLLTM ,世界上最小的可编程时钟 [1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock]
分类和应用: 时钟
文件页数/大小: 9 页 / 324 K
品牌: PLL [ PHASELINK CORPORATION ]
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(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
FEATURES
Designed for Very Low-Power applications
Offered in Tiny
GREEN/RoHS
compliant packages
o
6-pin DFN (2.0mmx1.3mmx0.6mm)
o
6-pin SC70 (2.3mmx2.25mmx1.0mm)
o
6-pin SOT23 (3.0mmx3.0mmx1.35mm)
Input Frequency:
o
Fundamental Crystal: 10MHz to 50MHz
o
Reference Input: 1MHz to 200MHz
Accepts >0.1V reference signal input voltage
Output Frequency:
o
<65MHz @ 1.8V operation
o
<90MHz @ 2.5V operation
o
<125MHz @ 3.3V operation
Disabled outputs programmable as HiZ or Active Low.
Low current consumption:
o
<1.2mA @ 27MHz
o
< 5 A when PDB is activated
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-28 consumes very low-power while
producing high performance clock outputs of up to
55MHz. Designed for low-power applications with
very stringent space requirement, PL611s-28
consumes about 1.2mA, while producing 2 distinct
outputs of 27MHz and 13.5MHz. Designed to fit in a
small SOT, SC70, or SOT23 package for high
performance applications, the PL611s-28 offers
excellent phase noise and jitter performance. The
power down feature of PL611s-28, when activated,
allows the IC to consume less than 5 A of power,
while its programming flexibility allows generating
any output, using a low-cost crystal or reference
input. In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(F
OUT
, F
REF
, F
REF
/2) output.
PACKAGE PIN CONFIGURATION
GND
XIN/FIN
OE, PDB, FSEL, CLK1
GND
1
2
3
6
5
4
CLK0
VDD
XOUT
OE, PDB,
FSEL, CLK1
GND
XIN/FIN
1
2
3
6
5
4
CLK0
VDD
XOUT
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
1
2
3
6
5
4
XOUT
VDD
CLK0
OE, PDB,
FSEL, CLK1
XIN/FIN
DFN-
DFN-6L
mmx1 mmx0 mm)
(2.0mmx1.3mmx0.6mm)
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
F
ref
R-counter
(8-Bit)
OSC
M-counter
(11-Bit)
Programmable
CLoad
Programmable Function
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 3/9/07 Page 1
PL611s-28
SC70-
SC70-6L
70
mmx2 25mmx mm)
mmx1
(2.3mmx2.25mmx1.0mm)
SOT23-
SOT23-6L
23
mmx3 mmx1 35mm
mm)
(3.0mmx3.0mmx1.35mm)
Phase
Detector
Charge
Pump
Loop
Filter
Fvco= Fref * (2 * M / R)
VCO
Fout= Fvco / (2 * P)
P-counter
(5-Bit)
CLK0
Programming
Logic
OE, FSEL,
PDB, CLK1