(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* (M / R) /(2*P)
Where M=16 bit
R= 7 bit
P= 4 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
•
•
•
•
•
OE - input
FSEL - input
PDB - input
CLK1 – output
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
VDD
SOT
Pin#
1
Pin #
SC70
Pin#
2
DFN
Pin#
3
Type
P
VDD connection.
Description
This programmable I/O pin can be configured as Output Enable (OE)
input, Power Down (PDB) input, Frequency Selector (FSEL) or CLK1
clock output. This pin has an internal 10M pull up resistor (OE, PDB &
FSEL Only).
OE, PDB,
FSEL, CLK1
2
1
2
I/O
The OE and PDB features can be programmed to allow the output
to float (Hi Z), or to operate in the ‘Active low’ mode.
State
0
1 (default)
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Frequency ‘2’
Frequency ‘1’
FIN
LF
GND
CLK0
3
4
5
6
3
4
5
6
1
6
5
4
I
I
P
O
Reference input pin.
Loop Filter input pin.
GND connection
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 2
PLL [ PHASELINK CORPORATION ]
