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PL611S-27-XXXGCR 参数 Datasheet PDF下载

PL611S-27-XXXGCR图片预览
型号: PL611S-27-XXXGCR
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V至3.3V PicoPLLTM可编程时钟 [1.8V to 3.3V PicoPLLTM Programmable Clock]
分类和应用: 时钟
文件页数/大小: 9 页 / 213 K
品牌: PLL [ PHASELINK CORPORATION ]
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(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
FEATURES
Advanced One Time Programmable (OTP) PLL design
Programmable PLL or direct oscillation operation
Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
Output Frequency up to
o
65MHz @ 1.8V operation
o
9/MHz @ 2.5V operation
o
125MHz @ 3.3V operation
Reference Input Frequency: 1MHz to 200MHz
Accepts >0.1V reference signal input voltage
Low current consumption, <10 A when PDB is
activated
One programmable I/O pin can be configured as
Output Enable (OE), Frequency Switching
(FSEL), or Power Down (PDB) input.
Disabled outputs programmable as HiZ or Active Low.
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from 0°C to 70°C
Available in 6-pin SOT23 & DFN
GREEN/RoHS
Compliant packages
DESCRIPTION
The PL611s-27 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLL
product family. Designed to fit in a small 6-pin DFN,
or 6-pin SOT package for high performance
applications, the PL611s-27 offers very low phase
noise, jitter, and power consumption, while offering 2
clock outputs. The Frequency Switching (FSEL)
capability of PL611s-27 allows for programming two
sets of frequencies, while the power down feature of
PL611s-27, when activated, allows the IC to
consume less than 10 A of power. PL611s-27’s
programming flexibility allows generating any output
using a Reference input signal.
PACKAGE PIN CONFIGURATION
CLK1
PL611s-27
1
2
3
6
5
4
CLK0
VDD
OE, PDB, FSEL
PL611s-27
FIN
CLK1
GND
1
2
3
6
5
4
OE, PDB, FSEL
VDD
CLK0
GND
FIN
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
mmx1 mmx0 mm)
SOT23-
SOT23-6L
23
(3.0mmx3.0mmx1.35mm)
mmx3 mmx1 35mm)
mm
BLOCK DIAGRAM
FIN
F
ref
R-counter
(8-Bit)
M-counter
(11-Bit)
Phase
Detector
Charge
Pump
Loop
Filter
Fvco= Fref * (2 * M / R)
VCO
P-counter
(5-Bit)
Fout=F
VCO
/(2*P)
CLK1
CLK0
Programmable Function
Programming
Logic
OE, PDB,
FSEL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/25/07 Page 1