(Preliminary)
PL611s-06
Low-Power Programmable Quick Turn Clock
T M
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
OE - input
•
CLK1 – output
PACKAGE PIN ASSIGNMENT
Name
Pin Assignment
SOT23
SC70
DFN
Pin #
Pin#
Pin#
1
2
2
Type
Description
This programmable I/O pin can be configured as an
Output Enable (OE) input, or CLK1 output. This pin
has an internal 60K pull up resistor (OE Function
Only).
GND connection
Crystal or Reference input pin
Crystal Output pin
XOUT
VDD
CLK0
4
5
6
4
5
6
6
5
4
O
Do Not Connect (DNC ) when FIN is present
P
O
VDD connection
Programmable Clock Output
OE, CLK1
B
GND
XIN, FIN
2
3
1
3
3
1
P
I
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
PLL [ PHASELINK CORPORATION ]
