(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
PACKAGE PIN ASSIGNMENT
Package Pin #
Name
XIN, FIN
Type
Description
Crystal or Reference Clock input
MSOP-10L SOP-8L
10
1
I
- Programmable Clock (CLK4) output or
- Configuration Switching input
CLK4, CSEL
2
-
B*
- Programmable Clock (CLK2) output, or
- Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input
CLK2, OEM,
PDB
3
2
B*
VDD
4, 8
5
3, 7
P
O
B*
P
VDD connection
CLK3
CLK0
GND
-
Programmable Clock (CLK3) output
Programmable Clock (CLK0) output
GND connection
6
4
5
6
8
1
CLK1
XOUT
7
O
O
Programmable Clock (CLK1) output
Crystal output pin. Do Not Connect when using FIN
9
* Note: All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor except when PDB mode is used. In
configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor.
KEY PROGRAMMING PARAMETERS
CLK[ 0:4 ]
Output Frequency
Output Drive Strength
Programmable Input/Output
CLK[0]
FVCO2 / P
Each output has
three optional drive
strengths to choose
from. They are:
Most pins are multi-function I/Os and can be
configured as:
CLK[1]
OEM – (Master OE controlling all outputs)
CSEL – (Device Configuration Switching)
PDB – (Power Down)
CLK[0:4] – (Output)
HiZ or Active Low disabled state
FVCO1 / (P*(1,2,4,8)) or FREF / (P*(1,2,4,8))
CLK[2]
FREF / (P*(1,2,4,8))
Low: 4mA
Std: 8mA (default)
High:16mA
CLK[3]
FVCO2 / (P*(1,2,4,8)) or FREF / (P*(1,2,4,8))
CLK[4]
FREF / P
Where FVCO = FREF * M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 2
PLL [ PHASELINK CORPORATION ]
