Analog Frequency Multiplier
PL660 and PL663 XO Families
L 2 X
O E
X IN
Q B A R
Q
F re q u e n c y
X 2
O s c illa to r
A m p lifie r
R
F re q u e n c y
X 4
X O U T
O n ly re q u ire d in x 4 d e s ig n s
L 4 X
Figure 2: Block Diagram of AFM XO
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while
Figure 4 shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e.
low jitter).
Figure 3: Period Jitter Histogram at 212.5MHz
Analog Frequency Multiplier (2x),
with 106.25 MHz crystal
Figure 4: Spectrum Analysis at 212.5MHz
Analog Frequency Multiplier (2x),
with sub-harmonics below –69 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
OE
Output State
0 (Default)
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
0 (Default)
1
0
PECL
1
0 (Default)
1
1 (Default)
0
1 (Default)
0 (Default)
1
LVDS or CMOS
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.]
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 2
PLL [ PHASELINK CORPORATION ]
