(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
OUTPUT ENABLE LOGICAL LEVELS
Part #
PL680-38 (PECL)
PL680-37 & 39 (CMOS or LVDS)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PIN DESCRIPTIONS
Name
VDDANA
XIN
XOUT
SEL2
OE_CTRL
DNC
GNDANA
LP
LM
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
SEL1
SEL0
TSSOP
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3x3mm QFN
Pin number
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
Type
P
I
O
I
I
-
P
-
-
P
O
P
O
P
I
I
VDD for analog Circuitry.
Description
Crystal input pin. (See Crystal Specifications on page 3).
Crystal output pin. (See Crystal Specifications on page 3).
Output frequency Selector pin.
Output enable control pin. (See OE_CTRL Logic Levels on page
1).
Do Not Connect
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GND connection for output buffer circuitry.
PECL or LVDS output.
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
Complementary PECL, LVDS output; Or single ended CMOS
output.
GND connection for output buffer circuitry.
Output frequency Selector pin.
Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 2
PLL [ PHASELINK CORPORATION ]
