PLL103-11
Low Skew Buffers
FEATURES
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Generates 13 copies of High-speed clock inputs.
Supports up to three SDRAM DIMMS synchronous
clocks.
Supports 2-wire I2C serial bus interface with
readback.
50% duty cycle with low jitter.
Less than 5ns delay.
Skew between any outputs is less than 250 ps.
Tri-state pin for testing.
Frequency up to 150 MHz.
3.0V-3.7V Supply range.
Available in 28-pin 300mil SOIC package.
PIN CONFIGURATION
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD1
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM7
SDRAM6
GND
GND1
SCLK
PLL103-11
BLOCK DIAGRAM
SDRAM0
SDATA
SCLK
I2C
Control
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
BUF_IN
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM1
POWER GROUP
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VDD: SDRAM (0:12)
VDD1: I2C Circuitry
GROUND GROUP
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GND: SDRAM (0:12)
GND1: I2C Circuitry
KEY SPECIFICATIONS
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BUF_IN to SDRAM outputs Delay: 1 ~ 5 ns.
Output Slew:
≥1.5
V/ns.
Output Skew:
±250
ps.
Output Duty Cycle: 50%
±
5%.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 1