PLL102-10
Low Skew Output Buffer
3. Switching Characteristics
PARAMETERS
Output Frequency
Duty Cycle
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
Jitter; Absolute Jitter
Jitter; 1-sigma
SYMBOL
t1
DC
T
r
T
f
T
skew
T
delay
T
dsk-dsk
T
cyc-cyc
T
lock
T
jabs
T
j1-s
DESCRIPTION
Measured at VDD/2,
C
L
=15pF, F
out
= 100MHz
Measured between 10%
and 90%VDD, C
L
=15pF
Measured between 90%
and 10%, C
L
=15pF
All outputs equally loaded,
C
L
=15pF
Measured at VDD/2
Measured at V
DD
/2 on the
CLKOUT pins of devices
Measured at 100MHz
Stable power supply, valid
clock presented on REF pin
At 10,000 cycles, low jitter
input signal
At 10,000 cycles, low jitter
input signal
MIN.
50
45
TYP.
50
1.2
1.2
MAX.
120
55
1.5
1.5
250
UNITS
MHz
%
ns
ns
ps
ps
ps
ps peak
ms
ps
ps
0
0
±350
700
60
1.0
20
9
50
15
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
VDD/2
Output - Output Skew
Output
VDD/2
Output
T
SKEW
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/17/05 Page 3
PLL [ PHASELINK CORPORATION ]
