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PLL103-02XC 参数 Datasheet PDF下载

PLL103-02XC图片预览
型号: PLL103-02XC
PDF下载: 下载PDF文件 查看货源
内容描述: DDR SDRAM缓存的台式机有4个DDR DIMM内存 [DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS]
分类和应用: 动态存储器双倍数据速率PC
文件页数/大小: 7 页 / 144 K
品牌: PLL [ PHASELINK CORPORATION ]
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PLL103-02 Rev.D
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
FEATURES
Generates 24 output buffer from one input.
Supports up to four DDR DIMMS.
Supports 266MHz DDR SDRAM.
One additional output for feedback.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V Supply range.
Enhanced DDR Output Drive selected by I2C.
Available in 48 pin SSOP.
PIN CONFIGURATION
FBOUT
VDD2.5
GND
DDR0T
DDR0C
DDR1T
DDR1C
VDD2.5
GND
DDR2T
DDR2C
VDD2.5
BUF_IN
GND
DDR3T
DDR3C
VDD2.5
GND
DDR4T
DDR4C
DDR5T
DDR5C
VDD2.5
SDATA
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
N/C
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PD#
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
PLL103-02
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BLOCK DIAGRAM
DDR0T
SDATA
SCLK
I2C
Control
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
BUF_IN
DDR4C
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
PD#
Note:
#: Active Low
DESCRIPTIONS
The PLL103-02 Rev.D is designed as a 2.5V buffer
to distribute high-speed clocks in PC applications.
The device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS.
The PLL103-02 Rev.D can be used in conjunction
with the PLL202-04 or similar clock synthesizer for
the VIA Pro 266 chipset.
The PLL103-02 Rev.D also has an I2C interface,
which can enable or disable each output clock.
When power up, all output clocks are enabled (has
internal pull up).
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/11/01 Page 1