Preliminary
PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
PIN DESCRIPTIONS
Name
FBOUT
BUF_IN
PD
Number
1
13
44
Type
O
I
I
Description
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.
Reference input from chipset. 3.3V input for STANDARD SDRAM mode;
2.5V input for DDR-ONLY mode.
Power Down Control input. When low, it will tri-state all outputs.
SEL_DDR
56
I
Input configure for DDR-ONLY mode or STANDARD SDR mode.
1 = DDR-ONLY mode (when VDD3.3_2.5 select 2.5V);
0 = SDR mode (when VDD3.3_2.5 select 3.3V).
In DDR-ONLY mode, all outputs will be configured as DDR outputs.
In STANDARD SDR mode, pin 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21
and 22 will be configured as STANDARD SDR outputs, and pin 27,
28, 29, 30, 35, 36, 37, 38, 41, 42, 46, 47, 50, 51,52 and 53 will be
configured as DDR outputs.
These outputs provide True copies of BUF_IN.
These outputs provide complementary copies of BUF_IN.
When SEL_DDR=1, these outputs provide DDR mode outputs; when
SEL_DDR=0, these outputs provide standard SDRAM mode outputs.
Voltage swing depends on VDD3.3_2.5.
When SEL_DDR=1, these outputs provide complementary copies of
BUF_IN; when SEL_DDR=0, these outputs provide standard SDRAM
mode outputs. Voltage swing depends on VDD3.3_2.5.
When VDD=2.5V, SEL_DDR=1. DDR-ONLY mode is selected; when
VDD=3.3V, SEL_DDR=0. STANDARD SDRAM mode is selected.
2.5V power supply.
Ground.
DDR[6:13]T
DDR[6:13]C
DDR[0,1:5]T_SDRA
M [10,0,2,4,6,8]
DDR[0,1:5]C_SDRA
M [11,1,3,5,7,9]
VDD3.3_2.5
VDD2.5
GND
36,38,42,47,
51,53,27,29
35,37,41,46,
50,52,28,30
4,6,10,15,
19,21
5,7,11,16,
20,22
2,8,12,17,23
32,40,45,
49,55
3,9,14,18,
25,31,34,39,
43,48,54
O
O
O
O
P
P
P
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 2
PLL [ PHASELINK CORPORATION ]
