Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
FEATURES
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PLL clock distribution optimized for Double Data
Rate SDRAM application up to 266Mhz.
Distributes one clock Input to one bank of six
differential outputs.
Track spread spectrum clocking for EMI reduction.
Programmable delay between CLK_INT and CLK[T/C]
from –0.8ns to +3.1ns by programming CLKINT and
FBOUT skew channel, or from –1.1ns to +3.5ns if
additional DDR skew channels are enabled.
Two independent programmable DDR skew chan-
nels from –0.3ns to +0.4ns with step size
±100ps.
Support 2-wire I
2
C serial bus interface.
2.5V Operating Voltage.
Available in 28-Pin 209mil SSOP.
PIN CONFIGURATION
CLKCO
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
N/C
AVDD
AGND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
N/C
FB_INT
FB_OUTT
ADDR_SEL
CLKT3
CLKC3
GND
PLL102-109
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DESCRIPTIONS
The PLL102-109 is a zero delay buffer that distributes
a single-ended clock input to six pairs of differential
clock outputs and one feedback clock output. Output
signal duty cycles are adjusted to 50%, independent of
the duty cycle at CLK_INT. The PLL can be bypassed
for test purposes by strapping AV
DD
to ground.
BLOCK DIAGRAM
Programmable
Skew Channel
-600~+800ps
±200ps step
AV
DD
Programmable
Delay Channel
CLK_INT
(0~2.5ns)
+170ps step
PLL
FB_INT
AV
DD
-300~+400ps
±100ps step
Control
Logic
-300~+400ps
±100ps step
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
CLKT5
CLKC5
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 1
PLL [ PHASELINK CORPORATION ]
