PLL130-09
High Speed Translator Buffer to LVDS
FEATURES
•
•
•
•
•
Differential LVDS output
Single AC coupled input (min. 100mV swing).
Input range from DC to 1.0 GHz.
2.5V to 3.3V operation.
Available in 8-Pin SOIC or 3x3mm QFN.
PIN CONFIGURATION
(TOP VIEW)
GND
REF_IN
1
2
3
4
VDD
8
7
6
5
GND
VDD
GND
LVDS_BAR
VDD
PLL130-09
DESCRIPTION
The PLL130-09 is a low cost, high performance,
high speed, buffer that reproduces any input fre-
quency from DC to 1.0GHz. It provides a pair of
differential LVDS output. Any input signal with at
least 100mV swing can be used as reference
signal. This chip is ideal for conversion from sine
wave, TTL, CMOS, or PECL to LVDS.
GND
LVDS
VDD
11
GND
GND
GND
OE^
13
14
15
16
12
VDD
10
9
8
7
6
5
LVDS_BAR
VDD
LVDS
GND
PLL130-09
1
2
3
4
REF_IN
GND
GND
Note: ^ denotes internal pull up
BLOCK DIAGRAM
REF_IN
Input
LVDS_BAR
LVDS
Amplifier
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/09/04 Page 1
GND
PLL [ PHASELINK CORPORATION ]
