PLL130-07
High Speed Translator Buffer to CMOS (Selectable Drive)
FEATURES
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•
•
•
•
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CMOS output
Selectable Drive capability (15pF or 30pF
output load).
Single AC coupled input (min. 100mV swing).
Input range from DC to 200 MHz.
2.5V to 3.3V operation.
Available in 8-Pin SOIC and 3x3mm QFN.
PIN CONFIGURATION
(TOP VIEW)
GND
REF_IN
GND
VDD
1
2
3
4
8
7
6
5
DRIV_SEL^
VDD
GND
CLK_OUT
PLL130-07
DESCRIPTION
The PLL130-07 is a low cost, high performance,
high speed, buffer that reproduces any input fre-
quency from DC to 200MHz. It provides CMOS
output with 15pF output load drive capability.
Any input signal with at least 100mV swing can
be used as reference signal. This chip is ideal
for conversion from sine wave to CMOS.
GND
9
VDD
11
VDD
DRIV_SEL^
GND
GND
OE^
13
14
15
16
12
VDD
10
8
7
6
5
CLK_OUT
VDD
N/C
GND
PLL130-07
1
2
3
4
REF_IN
GND
GND
Note: ^ denotes internal pull up
BLOCK DIAGRAM
REF_IN
Input
Amplifier
CLK_OUT
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/09/04 Page 1
GND
PLL [ PHASELINK CORPORATION ]
