(Preliminary)
PLL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
FEATURES
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VCXO with Divider Selection (DIVSEL) input pin
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PLL500-15: ÷8, ÷16
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PLL500-16: ÷2, ÷4
VCXO output for the 1MHz to 18MHz range
16MHz to 36MHz fundamental crystal input.
Low phase noise (-130 dBc @ 10kHz offset
using a 35.328MHz crystal).
CMOS output with OE tri-state control.
Integrated high linearity variable capacitors.
12mA drive capability at TTL output.
± 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5V to 3.3V operation.
Available in 8-Pin SOIC, 6-pin SOT23
GREEN/
RoHS compliant packages, or DIE.
PIN CONFIGURATION
XIN
VCON
DIVSEL^
GND
1
2
3
4
8
7
6
5
XOUT
OE^
VDD
CLK
SOIC-8
PLL500-15/16
P500-15/16
1
2
3
6
5
4
XOUT
VDD
CLK
XIN
VCON
GND
DESCRIPTION
The PLL500-15/16 is a low cost, high performance
and low phase noise VCXO for the 1.0MHz to 18MHz
range, providing less than -130dBc at 10kHz offset
when using a 35.328MHz crystal. The very low jitter
(2.5 ps RMS period jitter) makes this chip ideal for
applications requiring voltage controlled frequency
sources. Input crystal can range from 16MHz to
36MHz (fundamental resonant mode).
SOT23-6*
^: Denotes internal Pull-up
*: SOT package offers single divider option only
DIVIDER SELECTION LOGIC LEVELS
Part #
PLL500-15
PLL500-16
DivSel State
1 (Default)
0
1 (Default)
0
Operation
÷16
÷8
÷4
÷2
BLOCK DIAGRAM
DIVSEL
XIN
VCXO
XOUT
VCON
Varicap
Selectable
Divider
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/12/06 Page 1
PLL [ PHASELINK CORPORATION ]
