PLL500-27/-37/-47
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
5. DC Specification
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
SYMBOL
I
DD
CONDITIONS
F
XIN
= 36MHz, 15pF output load
F
XIN
= 77MHz, 15pF output load
F
XIN
= 155MHz, 15pF output load
PLL500-27
MIN.
TYP.
5
10
15
MAX.
6
12
18
N/A
15
10
UNITS
mA
pF
pF
pF
V
V
V
V
Allowable output load
capacitance
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage at
CMOS level
Output drive current
Short Circuit Current
VCXO Control Voltage
ESD Protection
C
L
(Output)
V
DD
V
OH
V
OL
PLL500-37 and-47: Std drive
PLL500-37 and-47: High drive
2.25
I
OH
= -12mA
I
OL
= 12mA
I
OH
= -4mA
Standard drive at TTL level
High drive at TTL level
V
DD
– 0.4
12
36
17
51
±50
2.4
3.63
0.4
mA
mA
3.3
V
V
VCON
Human Body Model
0
2000
6. Crystal Specifications
PARAMETERS
Crystal Loading Rating (VCON = 1.65V)
Maximum Sustainable Drive Level
Operating Drive Level
Max C0 for PLL500-27
Max C0 for PLL500-37
Max C0 for PLL500-47
C0/C1
ESR
R
S
50
3.5
2.5
2
250
30
-
Ω
pF
SYMBOL
C
L
(xtal)
MIN.
TYP.
8.5
MAX.
UNITS
pF
200
µW
µW
Note:
The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 4
PLL [ PHASELINK CORPORATION ]
