PLL650-03
Low EMI Network LAN Clock
FEATURES
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PIN CONFIGURATION
XIN
XOUT/50MHz_OE*^
GND
VDD
50MHz/FS0*^
GND
50MHz/FS1*^
50MHz/FS2*
T
1
2
16
15
VDD
VDD
25MHz/100MHz
GND
GND
SDRAMx2
VDD
50MHz/SS0*
T
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
4 outputs fixed at 50MHz with output disable, 1 output
selectable at 25MHz or 100MHz with output disable
SDRAM selectable frequencies of 66.6, 75, 83.3, 100MHz
(Double Drive Strength).
Spread spectrum technology selectable for EMI
reduction from
±0.5%, ±0.75%
center for SDRAM and
CPU.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 16-Pin 150mil SOIC
.
PLL 650-03
3
4
5
6
7
8
14
13
12
11
10
9
Note:
SDRAMx2: Double Drive strength.
T
: Tri-Level input ^: Internal pull-up
resistor *: Bi-directional pin (input value is latched upon power-up).
DESCRIPTION
The PLL 650-03 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25.0 MHz crystal, and produces multiple output
clocks for networking chips, PCI devices, SDRAM, and
ASICs.
FREQUENCY TABLE
FS0
0
0
1
1
FS1
0
1
0
1
SDRAM
100MHz
SST
83.3MHz
SST
75MHz
SST
66.6MHz
SST
FS2
0
M
1
Pin 14
25MHz
Disable
100MHz
SST
SST: SST modulation applied
BLOCK DIAGRAM
4
XIN
XOUT
XTAL
OSC
50MHz
(can be disabled)
Control
Logic
FS (0:3)
1
SDRAM (66.6, 75, 83.3, 100MHz)
1
25MHz/100 MHz
(can be disabled)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
PLL [ PHASELINK CORPORATION ]
