PLL650-05
Low EMI Network LAN Clock
FEATURES
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PIN CONFIGURATION
XIN
XOUT/ENB_125M*^
GND
VDD
125MHz
GND
75MHz/FS1*^
ENB_75MHz^
1
2
16
15
VDD
VDD
25MHz/FS0*^
GND
GND
SDRAMx2
VDD
SS0
T
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
3 fixed outputs of 25MHz, 75Mhz and 125Mhz with
output disable
SDRAM selectable frequencies of 105, 83.3, 140MHz
(Double Drive Strength).
Spread spectrum technology selectable for EMI
reduction from
±0.5%, ±0.75%
center for SDRAM and
CPU.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 16-Pin 150mil SOIC
.
PLL 650-05
3
4
5
6
7
8
14
13
12
11
10
9
Note:
SDRAMx2: Double Drive strength.
T
: Tri-Level input ^: Internal pull-up
resistor *: Bi-directional pin (input value is latched upon power-up).
DESCRIPTION
The PLL650-05 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, this
device can produce multiple clock outputs from a 25.0MHz
crystal or reference clock. This makes the PLL650-05 an
excellent choice for systems requiring clocking for network
chips, PCI devices, SDRAM, and ASICs.
FREQUENCY TABLE
FS1
0
0
1
1
FS0
0
1
0
1
SDRAMX2
Tristate
140MHz
SST
83.3MHz
SST
105MHz
SST
BLOCK DIAGRAM
1
XIN
XOUT
XTAL
OSC
125MHz
(can be disabled)
1
Control
Logic
FS (0:1)
SDRAM (105, 83.3, 140MHz)
75 MHz
(can be disabled)
1
1
25MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
PLL [ PHASELINK CORPORATION ]
