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PLL702-01XC 参数 Datasheet PDF下载

PLL702-01XC图片预览
型号: PLL702-01XC
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器的基于PowerPC的应用 [Clock Generator for PowerPC Based Applications]
分类和应用: 时钟发生器PC
文件页数/大小: 8 页 / 271 K
品牌: PLL [ PHASELINK CORPORATION ]
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PLL702-01
Clock Generator for PowerPC Based Applications
FEATURES
PIN ASSIGNMENT (28 pin SSOP)
CPUDRV_SEL^
XIN
XOUT / ASIC2_OE*^
VDD_ANA
VDD_DIG
VDD_PC I
PCI /
PCI_SEL*
T
GND_PCI
GND_USB
VDD_USB
USB / USB_SEL*
T
1 CPU Clock output with selectable frequencies (50,
66, 75, 80, 83, 90, 100,125 or 133 MHz).
1 ASIC output clock (at CPU clock or CPU clock ÷ 2).
2 ASIC output clocks (at CPU clock) w/ output enable.
1 PCI output clock w/ output enable
1 Selectable 48, 30 or 12MHz (USB) output.
Selectable Spread Spectrum (SST) for EMI reduction
on ASIC and CPU.
PowerPC compatible output and drive CPU Clock.
Selectable reduced 67% drive strength on CPU Clock
Advanced, low power, sub-micron CMOS processes.
14.31818MHz fundamental crystal input.
3.3V and/or 2.5V operation.
Available in 28-Pin 209mil SSOP (QSOP)
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK_SEL0
T
CLK_SEL1
T
SSCO
^
SSC1
^
GND_ANA
GND_CPU
CP U
o
VDD_CPU
VDD_ASIC1
ASIC1
GND_ASIC1
^
ASIC1_SEL
GND_DIG
GND_ASIC2
PLL702-01
VDD_ASIC2
ASIC2 A
ASIC2 B
Note :
o
:
^: Internal pull-up resistor
Selectable reduced drive
strength
*: Bi-directional pin
T
Tri-level input
:
DESCRIPTION
The PLL702-01 is a low cost, low jitter, and high
performance clock synthesizer for generic PowerPC based
applications. It provides one CPU clock, three ASIC
outputs, one PCI output, and a selectable 48, 30 or 12MHz
(USB) output. The user can choose between 9 different
CPU clock frequencies, while the ASIC output can be
identical or half of the CPU frequency. Low EMI Spread
Spectrum Technology is available for the CPU, ASIC and
PCI clocks. The CPU drive strength is user selectable from
100% to 67%. All frequencies are generated from a single
low cost 14.31818MHz crystal. The CPU and ASIC clock
can be driven from an independent 2.5V power supply.
FREQUENCY TABLES
CLK_SEL1
CLK_SEL0
CPU
(MHz)
ASIC1 (MHz)
ASIC1_SEL
=1
ASIC1_SEL
=0
ASIC2
(MHz)
PCI* (MHz)
PCI_SEL
=0
PCI_SEL
=M
0
0
0
M
M
M
1
1
1
Notes:
0
M
1
0
M
1
0
M
1
50
66
75
80
83
90
100
125
133
50
66
75
80
83
90
100
125
133
25
33
37.5
40
41.5
45
50
62.5
66.5
50
66
75
80
83
90
100
125
133
62.5
66.7
62.5
66.7
66.7
66.7
66.7
62.5
65.5
31.25
33.35
31.25
33.35
33.35
33.35
33.35
31.25
32.75
When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When
CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification.
* PCI_SEL=1 sets the Tri-state (output disabled) mode of the output.
BLOCK DIAGRAM
USB_SEL
Control
Logic
PLL
USB
CPU_CLK
PLL
SST
DIV 2
ASIC2_OE
PCI
PCI_OE
Control
Logic
ASIC1
ASIC2(A:B)
XIN
XOUT
SSC(0:1)
CLK_SEL(0:1)
ASIC1_SEL
PCI_SEL
XTAL
OSC
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 1