VERSION 1.0
2002
PCI 9656
Connectivity
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64-bit, 66MHz PCI r2.2 compliant
Motorola PowerQUICC and
generic 32-bit, 66MHz local
bus modes
3.3V I/O, 5V tolerant bus
interfaces
PICMG 2.1 r2.0 Hot Swap Silicon
272-ball, 27 x 27 mm, 1.27 mm
pitch PBGA
Zero wait state burst operation
64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola
PowerQUICC
™
& Generic 32-bit, 66MHz Local Bus Designs
Maximum PCI Bandwidth for Your 32-bit Local Bus Applications
The PCI 9656 offers flexible connectivity and high performance I/O acceleration features
to enable leading edge PCI, CompactPCI, and embedded host designs.
Motorola
®
MPC 850/860 PowerQUICC Designs
The PCI 9656 is the perfect match for the industry leading 32-bit communication proces-
sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection
to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its
Data Pipe Architecture™ technology.
Generic 32-bit, 66MHz Local Bus Designs
The PCI 9656 provides direct connection to two generic industry standard interconnect
buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices rang-
ing from processors, to DSPs, to memories, to custom ASICs and FPGAs.
The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI
I/O with those devices.
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Performance
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PCI bus bursts to 528 MB/sec
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Local bus bursts to 264 MB/sec
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2 DMA Channels
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Block and Scatter/Gather transfers
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DMA descriptor ring management
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Demand Mode and EOT
Hardware controls
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Direct Master data transfers
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Generate any PCI transaction
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Read ahead and programmable
read prefetch counter
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Move Your 32-bit Local Bus Designs Up to
64-bit, 66MHz PCI Operation
As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX
continues to provide leading edge, high performance PCI I/O acceleration solutions. Based
on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of
enhancements for the needs of today's telecom, networking, and I/O adapter designs:
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Direct Slave data transfers
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Access 8-, 16-, and 32-bit local
bus devices
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Deferred reads, deferred writes,
read ahead, posted writes, pro-
grammable read prefetch counter
64-bit, 66MHz PCI operation
32-bit, 66MHz local bus operation
Dynamic DMA descriptor ring management with Valid bit semaphore control
PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit
Initialization, and Intially Not Responding Support
PCI Power Management r1.1 D3
COLD
Power Management Event (PME) generation
PCI arbiter supporting 7 external masters
Reset and interrupt pins configurable for embedded host applications
JTAG boundary scan
Control
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I2O r1.5 messaging unit
Eight mailbox and two
doorbell registers
PCI arbiter supports 7
external masters
Host mode reset/interrupt signal
configuration
PCI D3
COLD
Power Management
Event (PME) generation support
Serial EEPROM interface
JTAG boundary scan
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The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration.
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PLX [ PLX TECHNOLOGY ]
