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PEX8112 参数 Datasheet PDF下载

PEX8112图片预览
型号: PEX8112
PDF下载: 下载PDF文件 查看货源
内容描述: ExpressLane ™ PCI Express至PCI桥接器 [ExpressLane™ PCI Express to PCI Bridge]
分类和应用: PC
文件页数/大小: 2 页 / 112 K
品牌: PLX [ PLX TECHNOLOGY ]
 浏览型号PEX8112的Datasheet PDF文件第2页  
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Version 1.0 2007
PEX 8112
Features
General Features
o
Forward and Reverse bridging
o
144-ball BGA package with standard
1.0 mm pitch (13mm x 13mm)
o
161-ball BGA package with fine
0.65 mm pitch (10mm x 10mm)
o
Low power – 400 milliwatts
o
EEPROM configuration option with
SPI
o
Internal 8Kbyte shared RAM
o
1.5 V core supply voltage
o
JTAG
o
Four (4) GPIO pins for maximum
design flexibility
o
Extensive PME support including
D0 and D0
Active
, D1, D2 and D3
Hot
and D3
Cold
o
Lead-free packaging only
o
Industrial Temperature: -40 to +85ºC
Integrated PCI Express Interface
o
PCI Express Base 1.0a compliant
o
x1 Link, dual-simplex, 2.5 Gbps per
direction
o
One virtual channel
o
Automatic LVDS polarity reversal
o
128 byte maximum payload size
o
Link CRC
o
Link power management
o
Flow control buffering
o
PCI Express transaction queues for
eight (8) outstanding TLPs
PCI Interface
o
PCI v.3.0: 32 bits, up to 66 MHz
o
PCI Power Management 1.1
o
Internal arbiter supports up to 4
external masters; REQ#/GNT#
signals
o
3.3V I/O and 5V tolerant PCI
o
Message Signal Interrupt (MSI)
support
o
Provides PCI clock output
o
Four mailbox registers for messaging
o
VGA and ISA Enable registers for
legacy operation
ExpressLane™ PCI Express to PCI Bridge
Reversible Bridge in a Tiny Package
The PLX Technology PEX 8112 bridge enables designers to migrate legacy PCI bus
interfaces to the new advanced serial PCI Express. This is ideal for including
existing PCI ICs on a PCI Express™ Adapter Board, such as the new ExpressCard™
or AdvancedMC™ standards. The 13mm x 13mm standard BGA package or 10mm
x 10mm fine BGA package offerings makes the PEX 8112 bridge well suited for
applications where board real estate is at a premium. With its low power 0.15 micron
CMOS design, the PEX 8112 consumes only about 400 mW of power.
Forward and Reverse Bridging
The PEX 8112 supports
forward and reverse bridging
as defined by the
PCI Express-to-PCI/PCI-X Bridge Specification 1.0. In forward mode, the bridge
allows legacy PCI chips and adapters to be used with new PCI Express processor
systems. Reverse bridge operation allows conventional PCI processors and chipsets
to configure and control advanced PCI Express switches and endpoints. The reverse
PEX 8112 not only allows complete configuration of a downstream PCI Express
system from the PCI bus, but it also handles limited PCI Express root functions for
reverse interrupt and Power Management Events.
PCI Bus (32-bit, 33/66 MHz)
Block Diagram
The PEX 8112 is equipped with a
standard PCI Express port that
operates as a single, x1 link with a
maximum of 250 Megabytes per
second of throughput per transmit
and receive direction. The single 2.5
Gbps integrated SerDes delivers the
highest bandwidth with the lowest
possible pin count using LVDS
technology.
The PEX 8112 has a single parallel
bus segment supporting the PCI v.3.0
protocol, and a 32-bit wide parallel
data path running up to 66MHz.
The device supports internal queues
with flow control features to optimize
throughput and traffic flow.
PCI Master and Target Interface Logic
Configuration
Registers
FIFOs
8K Shared
RAM
PCI Express Transaction Layer
(Packet Construction Logic)
PCI Express Data Link Layer
PCI Express PHY Layer
j
PCI Express Link (1 lane, 2.5 GHz)
Figure 1. PEX 8112 Block Diagram