.
Version 1.4 2007
Features
PEX 8547 General Features
o
48-lane PCI Express switch
o
Three configurable ports
(x1, x2, x4, x8, x16)
o
Integrated SerDes
o
37.5mm x 37.5mm, 736 pin PBGA package
o
Typical Power: 4.9 Watts
PEX 8547
PCI Express™ Switch for Graphics Fan-Out
Multi-Purpose, Feature Rich PCI Express* ExpressLane™ Switch
PEX 8547 Key Features
o
Standards Compliant
-
PCI Express Base Specification, r1.1
o
High Performance
-
Packet Cut Through
-
Packet Latency of 110ns (x16 to x16)
-
Non-blocking Switch Fabric
-
Full Line rate
o
Flexible Configuration
-
Three configurable ports
-
Flexible lane width/port x1, x2, x4, x8, 16
-
Configurable with strapping pins,
EEPROM, Host software or I
2
C
-
Lane and polarity reversal
o
PCI Express Power Management
-
Link power management states: L0, L0s,
L1, L2/L3 Ready, and L3
-
Device states: D0 and D3hot
o
INTA and FATAL ERROR signal support
o
Port Status bits and GPO available
o
Quality of Service (QoS)
-
Eight Traffic Classes per port
-
Round Robin and Weighted RR port
arbitration
o
Reliability, Availability, Serviceability
(RAS)
-
Error reporting in addition to Advanced
Error Reporting support of PCI Express
-
Per port performance monitoring
•
Average packet size, number of
packets, CRC errors
•
JTAG boundary scan
The ExpressLane
PEX 8547
device offers PCI Express
switching
capability conforming to the latest revision of the PCI Express Base
specification (r1.1). This device enables users to add scalable high
bandwidth,
non-blocking
interconnects to high-end graphics
applications. The PEX 8547 is designed to support graphics or data
aggregation while supporting
peer-to-peer
traffic for high resolution
graphics applications.
High Performance
The ExpressLane PEX 8547 architecture supports packet
cut-through
with a latency of 110ns (x16 to x16).
This, combined with large
packet memory
(256 to 1024 byte maximum payload size)
and non-
blocking internal switch architecture, provide full line rate on its ports
for performance hungry applications such as storage servers or storage
switch fabrics.
Low Packet Latency
The PEX 8547 supports packet cut-through with a latency of 110ns
between symmetric (x16) ingress and egress ports. The low latency
enables many applications to achieve high throughput and
performance. In addition to low latency, the device supports a packet
payload size of up to 1024 bytes, enabling the user to achieve even
higher throughput.
Low Power with Granular SerDes Control
The ExpressLane PEX 8547 provides
low power
capability that is
fully compliant with the PCI Express power management
specification.
Interoperability
The ExpressLane PEX 8547 is designed to be fully compliant with the
PCI-SIG specification. Additionally, it supports auto-negotiation, lane
reversal, and polarity reversal.
Configuration Flexibility
The ExpressLane PEX 8547 provides several ways to configure its
operations. The device can be configured through strapping pins, I
2
C
interface, CPU configuration cycles, or an optional serial EEPROM.
This allows for easy debug during the development phase,
performance monitoring during the operation phase, and driver or
software upgrade.
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