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PEX8548-AA25BI 参数 Datasheet PDF下载

PEX8548-AA25BI图片预览
型号: PEX8548-AA25BI
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能48通道, 9端口PCIe交换器 [High-Performance 48-lane, 9-port PCIe Switch]
分类和应用: 总线控制器微控制器和处理器外围集成电路PC
文件页数/大小: 4 页 / 315 K
品牌: PLX [ PLX TECHNOLOGY ]
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Low Power with Granular SerDes Control
The PEX 8548 provides low power capability that is
fully compliant with the PCI Express power
management specification. In addition, the SerDes
physical links can be turned off when unused for even
lower power.
Flexible Port Width Configuration
The width of each port can be individually configured
through auto-negotiation, hardware strapping, host
software configuration, I
2
C interface, or through an
optional EEPROM.
The PEX 8548 supports a large number of port
configurations (see Figure 1). For example, if you are
using the PEX 8548 in a fan-out application, you may
configure the upstream port as a x16 and the
downstream as eight x4 ports; three x8 ports & two x4
ports; or various combinations, as long as you don’t run
out of lanes (48) or ports (9). For a dual-graphics
application, the device can be configured as three x16
ports.
x16
x16
advanced
error reporting
features make it suitable for
High Availability (HA) applications.
Three
downstream ports include a Standard Hot Plug
Controller. If the PEX 8548 is used in an application
where one or more of its downstream ports connect to
PCI Express slots, each port’s Hot Plug Controller can
be used to manage the hot-plug event of its associated
slot. Furthermore, its upstream port is a
hot-plug client,
allowing it to be
used on hot-pluggable adapter cards,
backplanes, and fabric modules.
Fully Compliant Power Management
For applications that require power management, the
PEX 8548 device supports both link (L0, L0s, L1, L2/L3
Ready, and L3) and device (D0 and D3hot) power
management states, in compliance with the PCI Express
power management specification.
SerDes Power and Signal Management
The PEX 8548 supports
software control
of the
SerDes
outputs
to allow optimization of power and signal
strength in a system. The PLX SerDes implementation
supports four levels of power – off, low, typical, and
high. The SerDes block also supports
loop-back modes
and
advanced reporting of error conditions,
which
enables efficient debug and management of the entire
system.
PEX 8548
PEX 8548
Applications
x8 x8 x4 x4 x4 x4
x8 x8 x8 x4 x4
x8
x16
Suitable for
host-centric
as well as
peer-to-peer traffic
patterns,
the PEX 8548 can be configured for a wide
variety of form factors and applications.
Host Centric Fan-out
The PEX 8548, with its symmetric or asymmetric lane
configuration capability, allows user-specific tuning to a
variety of host-centric applications.
PEX 8548
PEX 8548
all x8
x16
x16
Figure 1. Common Port Configurations
Low Packet Latency
The PEX 8548 supports packet
cut-thru
with a
maximum packet latency of 110ns between symmetric
x16 ingress and egress ports. The low latency enables
applications to achieve high throughput and
performance. In addition to low latency, the device
supports a packet payload size of up to 1024 bytes,
enabling the user to achieve even higher throughput.
Hot Plug for High Availability
Hot plug capability allows users to replace hardware
modules and perform maintenance without powering
down the system. The PEX 8548 hot plug capability and
End
Point
CPU
Chip
Set
x8 or x16
Memory
PEX 8548
x8
x8
x4
Figure 2. Fan-in/out Usage