Version 0.8 2007
Features
PEX 8624 General Features
o
24-lane, 6-port PCIe Gen2 switch
-
Integrated 5.0 GT/s SerDes
o
19 x 19mm
2
, 324-pin FCBGA package
o
Typical Power: < 4.0 Watts
PEX 8624
PCIe Gen2, 5.0GT/s 24-lane, 6-port Switch
The
ExpressLane
TM
PEX 8624 device offers PCI Express switching
capability enabling users to add scalable high bandwidth, non-blocking
interconnection to a wide variety of applications including
workstations, storage systems, and communications platforms.
The
PEX 8624 is well suited for
fan-out, aggregation, and peer-to-peer
applications.
High Performance & Low Packet Latency
The PEX 8624 architecture supports packet
cut-thru with a maximum
latency of 145ns (x8 to x8).
This, combined with large packet memory and
non-blocking internal switch architecture, provides full line rate on all ports
for performance-hungry applications such as
servers
and
switch fabrics.
The low latency enables applications to achieve high throughput and
performance. In addition to low latency, the device supports a
max payload
size of 2048 bytes,
enabling the user to achieve even higher throughput.
Data Integrity
The PEX 8624 provides
end-to-end CRC
(ECRC) protection and
Poison bit
support to enable designs that require
end-to-end data integrity.
PLX also
supports data path parity and memory (RAM) error correction as packets
pass through the switch.
Flexible Register & Port Configuration
The PEX 8624’s 6 ports can be configured to lane widths of x1, x2, x4, or
x8. Flexible buffer allocation, along with the device's
flexible packet flow
control,
maximizes throughput for applications where more traffic flows in
the downstream, rather than upstream, direction. Any port can be designated
as the upstream port, which
x4
x8
can be changed dynamically.
The PEX 8624 also provides
several ways to configure its
registers. The device can be
PEX 8624
PEX 8624
configured through strapping
pins,
I
2
C interface,
host
software, or an optional
x4 x4 x4 x4
5 x4
serial EEPROM. This allows
x8
x8
for easy debug during the
development phase,
performance monitoring
PEX 8624
during the operation phase,
PEX 8624
and driver or software
upgrade. Figure 1 shows
some of the PEX 8624’s
x8 x4 x4
x8
x8
common port configurations.
Figure 1. Common Port Configurations
PEX 8624 Key Features
o
Standards Compliant
-
PCI Express Base Specification, r2.0
(backwards compatible w/ PCIe r1.0a/1.1)
-
PCI Power Management Spec, r1.2
-
Microsoft Vista Compliant
-
Supports Access Control Services
-
Dynamic link-width control
-
Dynamic SerDes speed control
o
High Performance
-
Non-blocking switch fabric
-
Full line rate on all ports
-
Packet Cut-Thru with 145ns max packet
latency (x8 to x8)
-
2KB Max Payload Size
-
Read Pacing (bandwidth throttling)
-
Dual-Cast
o
Flexible Configuration
-
Ports configurable as x1, x2, x4, x8
-
Registers configurable with strapping
pins, EEPROM, I
2
C, or host software
-
Lane and polarity reversal
-
Compatible with PCIe 1.0a PM
o
Dual-Host & Fail-Over Support
-
Configurable Non-Transparent port
-
Moveable upstream port
-
Crosslink port capability
o
Quality of Service (QoS)
-
Eight traffic classes per port
-
Weighted round-robin source
port arbitration
o
Reliability, Availability, Serviceability
-
3 Hot Plug Ports with native HP Signals
-
All ports hot plug capable thru I
2
C
(Hot Plug Controller on every port)
-
ECRC and Poison bit support
-
Data Path parity
-
Memory (RAM) Error Correction
-
INTA# and FATAL_ERR# signals
-
Advanced Error Reporting
-
Port Status bits and GPIO available
-
Per port error diagnostics
-
Performance Monitoring
•
Per port payload & header counters
-
JTAG AC/DC boundary scan
Preliminary - PLX Confidential
PLX [ PLX TECHNOLOGY ]
