PMC
FEATURES
•
Single Power Supply Operation
- 5.0 V ± 10% Read/Program/Erase
• High Performance Read
- 55/70/90 ns access time
• Cost Effective Block Architecture
- One 16 Kbytes top or bottom Boot Block with
software lockout
- Two 8 Kbytes Parameter Blocks
- One 96 Kbytes Main Block
- One 128 Kbytes Main Block
• Automatic Erase and Program
-
Typical 15
µs/byte
programming
- Typical 40 ms block or chip erase
• Hardware Data Protection
ADVANCE INFORMATION
Pm29F002
2 Megabit (256K X 8) 5.0 Volt-only CMOS Flash Memory
• Data# Polling and Toggle Bit Features
• Low Power Consumption
- Typical 10 mA active read current
- Typical 40 mA program/erase current
- Typical <0.1
µA
CMOS standby current
• High Product Endurance
- Guarantee 10,000 program/erase cycles
- Typical 50,000 program/erase cycles
- Minimum 10 years data retention
• Industrial Standard Pin-out and Packaging
- 32-pin Plastic DIP
- 32-pin PLCC
• Manufactured on 0.30 µm process
- Fully compatible with previous 0.35 µm version
GENERAL DESCRIPTION
The Pm29F002 is a 2 Megabit, 5.0 Volt-only Flash Memory organized as 262,144 bytes of 8 bits each.
This device is designed to use a 5.0 Volt power supply to perform in-system programming, 12.0 Volt V
PP
power
supply for program and erase operation is not required. The device can be programmed in standard EPROM
programmers as well.
The 2 Megabit memory array is divided into five blocks of one 16 Kbytes, two 8 Kbytes, one 96 Kbytes, and
one 128 Kbytes for BIOS and parameters storage. The five blocks allow users to flexibly make chip erase or
block erase operation flexible. The block erase feature allows a particular block to be erased and reprogrammed
without affecting the data in other blocks. After the device performed chip erase or block erase operation, it can
be reprogrammed on a byte-by-byte basis.
The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible
pin-out and command set. The program operation of Pm29F002 is executed by issuing the program command
code into command register. The internal control logic automatically handles the programming voltage ramp-up
and timing. The erase operation of Pm29F002 is executed by issuing the chip erase or block erase command
code into command register. The internal control logic automatically handles the erase voltage ramp-up and
timing. The preprogramming on the array which has not been programmed is not required before the erase
operation. The device also features Data# Polling and Toggle Bit function, the end of program or erase operation
can be detected by Data# Polling of I/O7 or Toggle Bit of I/O6.
The device has an optional 16 Kbytes top or bottom boot block with a software lockout feature for data
security. The boot block can be used to store user secure code. When the lockout feature is enabled, the boot
block is permanently protected from being reprogrammed.
The Pm29F002 is manufactured on PMC’s 0.30 µm advanced nonvolatile technology, P-FLASH™. The
device is packaged in a 32-pin DIP and PLCC with access time of 55, 70 and 90 ns.
Programmable Microelectronics Corp.
1
Issue Date: March, 2001 Rev:1.0
PMC [ PMC-SIERRA, INC ]
