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PM49FL002T-33VCE 参数 Datasheet PDF下载

PM49FL002T-33VCE图片预览
型号: PM49FL002T-33VCE
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位/ 4兆位3.3伏,只有固件集线器/ LPC闪存 [2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory]
分类和应用: 闪存内存集成电路光电二极管PC
文件页数/大小: 46 页 / 208 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC
FEATURES
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Single Power Supply Operation
Low voltage range: 3.0 V - 3.6 V
Standard Intel Firmware Hub/LPC Inter-
face
Read compatible to Intel
®
82802 Firmware
Hub devices
Conforms to Intel LPC Interface Specification
Revision 1.1
Memory Configuration
Pm49FL002: 256K x 8 (2 Mbit)
Pm49FL004: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
Pm49FL002 / Pm49FL004
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
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Firmware HUB (FWH)/Low Pin Count
(LPC) Mode
33 MHz synchronous operation with PCI bus
5-signal communication interface for in-
system read and write operations
Standard SDP Command Set
Data# Polling and Toggle Bit features
Register-based read and write protection for
each block (FWH mode only)
4 ID pins for multiple Flash chips selection
(FWH mode only)
5 GPI pins for General Purpose Input Register
TBL# pin for hardware write protection to Boot
Block
WP# pin for hardware write protection to whole
memory array except Boot Block
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Address/Address Multiplexed (A/A Mux)
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Mode
11-pin multiplexed address and 8-pin data I/O
interface
Supports fast programming on EPROM
programmers
Standard SDP Command Set
Data# Polling and Toggle Bit features
Top Boot Block
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Pm49FL002: 16 Kbyte top Boot Block
Pm49FL004: 64 Kbyte top Boot Block
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Automatic Erase and Program Operation
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Build-in automatic program verification for
extended product endurance
Typical 25 µs/byte programming time
Typical 50 ms sector/block/chip erase time
Lower Power Consumption
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Typical 2 mA active read current
Typical 7 mA program/erase current
Two Configurable Interfaces
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In-System hardware interface: Auto detection
of Firmware Hub (FWH) or Low Pin Count
(LPC) memory cycle for in-system read and
write operations
Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
High Product Endurance
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Guarantee 100,000 program/erase cycles per
single sector (preliminary)
Minimum 20 years data retention
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Compatible Pin-out and Packaging
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32-pin (8 mm x 14 mm) VSOP
32-pin PLCC
Optional lead-free (Pb-free) package
Hardware Data Protection
Programmable Microelectronics Corp.
PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
1
Issue Date: December, 2003 Rev:1.4