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PM5319 参数 Datasheet PDF下载

PM5319图片预览
型号: PM5319
PDF下载: 下载PDF文件 查看货源
内容描述: 对于622和155 Mbit / s的SONET / SDH接口 [SONET/SDH Interface for 622 & 155 Mbit/s]
分类和应用:
文件页数/大小: 2 页 / 46 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM5319的Datasheet PDF文件第2页  
PM5319
ARROW 622
Released
SONET/SDH Interface for 622 & 155 Mbit/s
FEATURES
SONET/SDH INTERFACE
• Interface rate software selectable
between OC-3/STM-1 (155.52 Mbit/s)
and OC-12/STM-4 (622.08 Mbit/s)
rates
• Integrated clock recovery & synthesis
allows direct interface to low-cost
optical transceivers
• Integrated clock synthesis generates
line clock from 77.76 MHz reference
• Complies with Bellcore, ANSI, and ITU
specifications for Jitter Tolerance and
Jitter Generation
• High order path processing and
alignment to STS-1/AU-3/TU-3 level
• Full access to all SONET/SDH
Transport overhead bytes via a
dedicated serial port
• Full access to all SONET/SDH STS-
1/AU-3/TU-3 path overhead bytes via a
dedicated serial port
• Full access to all DCC bytes via a
dedicated serial interface
• Ring Control port provides real time
detection of error conditions and
insertion of alarms such as AIS & RDI
• Section and Path Trace filter and
monitor checks for Trace Identifier
Mismatch (TIM) and Trace Identifier
Unstable (TIU) conditions
GENERAL FEATURES
• Provides an industry standard 8-bit,
77.76 MHz telecombus interface
• Multi-drop capability allows multiple
devices to share the add/drop bus for
redundancy or multiplexing purposes
• Full Time Slot Interchange (TSI) allows
flexible mixing of traffic from the
SONET/SDH and DS3/E3/EC-1
Interfaces
• Supports diagnostic 2
23
-1 pseudo-
random bit-sequence (PRBS)
generation and monitoring
• Provides a standard JTAG test-port for
boundary scan board-test purposes
• Provides a generic 16-bit
microprocessor interface for control
and monitoring
• 15x15mm 196 ball CABGA package
allows for flexible placement and
routing
DS3/E3/EC-1 INTERFACE
• Flexible three-port DS3/E3/EC-1
Interface
• Supports clear channel
mapping/demapping of DS3 or E3
into/from STS-1, AU-3, or TU-3
• Fully digital desynchronizers require
no external PLLs for standards-
compliant operation
• Integrated desynchronization CSU
allows low rate reference clock at
44.736 MHz, 34.368 MHz, or 51.84
MHz
• Bi-directional digital jitter attenuation
for DS3 and E3 streams allows
interfacing to low cost LIUs
• Full bi-directional performance
monitoring for DS3, E3, and EC-1
streams
• Full access to DS3/E3/EC-1 Overhead
bytes
APPLICATIONS
SONET/SDH Add/Drop Multiplexers
Terminal Multiplexers
Customer Premise Equipment
Media Gateways
Multiservice Provisioning Platforms
Channelized Router Interfaces
Digital Cross-Connects
BLOCK DIAGRAM
PMON
DS3 PRBS
Generator
& Checker
DS3/E3/EC-1
Overhead
Insert/Extract
Microprocessor
Interface
JTAG
Interface
Clock + Data
Interface
to LIU
DS3/E3/EC-1Interface (x3)
Interface
DS3/E3/EC-1
Interface (x3)
(x3)
DS3/E3/EC-1
Telecom Bus Interface
DS3
Framer
E3
Framer
EC-1
Section/
Line/Path
Bit Error
Rate
Monitor
Rx TSI
8x77.76 MHz
Multi-drop
Telecom Bus
Framer
Path
Processor
TU3 Path
Processor
Aligner
TxTSI
Serial PECL Interface
to 155 or 622 Mbit/s
Optical Transceiver
SONET/SDH Interface
PRBS
Generator
& Checker
Ring Control
Port
Alarm
Processing
Bit Error
Rate
Monitor
SONET/SDH
Overhead
Insert/Extract
PMC-2030426
Issue 3
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2004
All rights reserved.