PMC-Sierra, Inc.
S
TANDARD
P
RODUCT
PM5346 S/UNI-LITE
ISSUE 6
SATURN USER NETWORK INTERFACE
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PIN DESCRIPTION
Pin
Name
RATE1
RATE0
Pin
No.
97
98
Type
Input
Function
The RATE1 and RATE0 inputs select the frame format
and line rate for both transmit and receive:
RATE[1:0]
11
10
01
00
155.52 Mbit/s, STS-3c/STM-1
transmission convergence (TC)
51.84 Mbit/s, STS-1 TC
25.92 Mbit/s, STS-1 TC
12.96 Mbit/s, STS-1 TC
The RATE1 and RATE0 inputs have integral pull up
resistors so the default is STS-3c/STM-1.
RBYP
Input
41
The receive bypass (RBYP) input must be tied low for
proper operation. RBYP has an integral pull down
resistor.
The receive differential data inputs (RXD+, RXD-)
contain the NRZ bit serial receive stream. The
receive clock is recovered from the RXD+/- bit stream.
RXD+/- must be connected to a differential data
source, single-ended operation is not supported for
these inputs.
The receive differential data outputs (RXDO+, RXDO-)
are provided to allow decision feedback equalization
(DFE) to correct baseline wander. It is intended that
these outputs be low pass filtered and attenuated to
create an appropriate correction signal that is
summed with incoming data to recover the D.C.
component. RXDO+/- are retimed (sampled by the
recovered clock) versions of the RXD+ and RXD-
inputs. RXDO+/- are squelched (RXDO+ is forced low
and RXDO- is forced high) when loss of signal
(ALOS+/-) is asserted.
The receive differential reference clock inputs
(RRCLK+, RRCLK-) contain a jitter-free 19.44 MHz or
6.48 MHz reference clock.
RXD+
RXD-
PECL
Input
26
25
RXDO+
RXDO-
Output
22
23
RRCLK+
RRCLK-
PECL
Input
34
33
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9
PMC [ PMC-SIERRA, INC ]
