PRODUCTION
S/UNI-622-POS
DATASHEET
PMC-1980911
ISSUE 5
PMC-Sierra, Inc.
PM5357
S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
ISSUE
4
DATE
Dec, 1999
DETAIL
#1. Modified section 9.5 (UTOPIA and POS-PHY pin
description) and section 14.4 (Functional timing) to reflect
operation of the RPA signal (Receive POS-PHY L2 operation
requires data be qualified by RVAL).
#2 DC characteristics update (Section 16)
#3 Registers updated with correct defaults and descriptions:
Register 0X01, Bit 4 (TFPEN), Defaults To 1, Not 0
Register 0X08, Description Incorrect
Register 0X09 Description Incorrect
Register 0XC1, Bit 1 (DSCR), Defaults To 1, Not 0
Register 0XC4, Bit 3 (TPAHWM), Defaults To 0, Not 1
New Register 0XFC: Concatenation Status And Enable
New Register 0XFD: Concatenation Interrupt Status
New Register Bit Required For OC-3 Operation (Register 0X07)
Register 0X5E Bit 5 (RTYPE) To Enable LAN Or WAN
Performance
Register 0X00 Type Bits Incorrect
Loss Of Multi-frame Tributary AIS (LOMTUAIS) Bit 2 Incorrectly
Stated In Register 0X0D
#4 APS pin description modified
#5 Documented overflowing Transmit FIFO
#6 Updated TFCLK timing specifications, RFCLK timing
specifications
#7 Diagnostic Loop-back Clarification
#8
Bit Error Rate Monitor Table Update
#9
Receive Data Requires 3 RFCLK Cycles Before
Becoming Valid (Utopia Level 3 Only)
#10
TPAHWM Upper Limit
#11 Receive Line AIS Insertion Is Not Gated By ALLONES
#12 Large Power Supply Glitch (Beyond Specification) Can
Cause Clock Synthesis Unit To Lose Lock To Reference.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
