PMC-Sierra,Inc.
Preliminary
PM5381
S/UNI®-2488
SATURN® User Network Interface for 2488 Mbit/s
FEATURES
• Single chip ATM and POS User-
Network Interface operating at 2488.32
Mbit/s.
• Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT
Recommendation I.432.
• Implements the Point-to-Point Protocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the Internet
Engineering Task Force (IETF).
• Processes bit-serial 2488.32 Mbit/s
STS-48 (STM-16-16c) data streams
with on-chip clock and data recovery
and clock synthesis.
• Complies with Bellcore GR-253-CORE
jitter tolerance, jitter transfer and
intrinsic jitter criteria.
• Provides termination for SONET
Section, Line and Path overhead or
SDH Regenerator Section, Multiplexer
Section and High Order Path
overhead.
• Provides UTOPIA Level 3 32-bit wide
System Interface (clocked up to
104 MHz) with parity support for ATM
applications.
• Provides SATURN POS-PHY
Level 3™ 32-bit System Interface
(clocked up to 104 MHz) for Packet
over SONET (POS), or ATM
applications.
• Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from
the line side transmit stream to the line
side receive stream interface.
• Provides support for automatic
protection switching including a bi-
directional 4-bit LVDS 777.76 MHz
port.
• Provides a standard five signal IEEE
1149.1 JTAG test port for boundary
scan board test purposes.
• Provides a generic 16-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
ROHCLK ROHRP
RTOH
RPOH RPOHEN B3E
BLOCK DIAGRAM
APSI+/-[4:1]
Rx APS Sync
Extractor &
Bit Error
Monitor
Section
Trace
Processor
Rx LVDS
Interface
Path
Trace
Processor
Rx APS
UTOPIA
Level 3 /
POS Level
3 Receive
Interface
RENB
RCA/RVAL
RSOC/RSOP
RPRTY
RDAT[31:0]
RFCLK
REOP
RERR
RSX
RMOD[1:0]
SONET/SDH
Alarm
Reporting
Controller
SALM
RALM
POSL3_UL3B
TENB
TCA/PTPA
UTOPIA
Level 3 /
POS Level
3 Transmit
Interface
TSOC/TSOP
TPRTY
TDAT[31:0]
TFCLK
TEOP
TERR
TMOD[1:0]
Tx APS
Path
Trace
Processor
Microprocessor
Interface
APSIFP
PGMRCLK
Rx Line
Interface
RX
Transport
O/H
Processor
FIFO
Rx Path O/H
Processor
Rx Telecom
Aligner
ATM/HDLC
Processor
SD
RXD+/-
OOF
RCLK
PRBS
Generator/
Monitor
TCLK
TXD+/-
REFCLK+/-
Tx Line
Interface
PGMTCLK
Tx
Transport
O/H
Processor
Tx Path
O/H
Processor
ATM/HDLC
Processor
FIFO
C0 C1
C2 C3
Analog
RES_RESK
ATP[3:0]
Section
Trace
Processor
JTAG
Tx LVDS
Interface
TRSTB
TPOHRDY
APSO+/-[4:1]
D[15:0]
A [13:0]
CSB
WRB
RDB
RSTB
TDO
TMS
TCK
ALE
TDI
TOHCLK TOHFP
TTOH TTOHEN
APSMODE
APSOFP
PMC-2000453 (p2)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
TPOH TPOHEN
INTB
© Copyright PMC-Sierra, Inc. 2000
PMC [ PMC-SIERRA, INC ]
