Advance
PM5390
S/UNI®-9953
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet
GENERAL DESCRIPTION
• The S/UNI-9953 is a single chip ATM,
POS and 10 Gigabit Ethernet User-
Network Interface operating at 9953.28
Mbit/s and 10.3 Gbit/s. The S/UNI
9953 is intended for use in OC-192c
and high-density OC-48c POS/ATM
applications as well as 10 Gigabit
Ethernet WAN and LAN PHY port
cards.
4 x STS-48c (4 x STM-16-16c).
•
STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
• Supports alarm signal
insertion/detection, B1/2/3 processing
and insertion/termination of SONET
Section/Line/Path overhead bytes (or
SDH equivalents).
• Provides ATM and POS payload
processing for:
•
STS-192c (STM-64-64c)
•
4 x STS-48c (4 x STM-16-16c).
•
STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
•
POS/ATM
• Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT Rec. I.432.
• Implements the Point-to-Point Protocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the Internet
Engineering Task Force (IETF).
10 GIGABIT ETHERNET
• Implements 10 Gigabit Ethernet WAN
and LAN PHY according the IEEE
P802.3ae standard currently under
development.
• Provides standard IEEE P802.3ae 10
Gigabit Ethernet Media Access
Controller (10GMAC) for frame
verification.
• Implements IEEE P802.3ae 64B/66B
Physical Coding Sub-layer (PCS).
FEATURES
• Provides WAN Interface Sub-layer
(WIS), Physical Coding Sub-layer
(PCS), and Media Access Controller
(MAC) functionality for OC-192c rate
10 Gigabit Ethernet WAN PHY
datastream.
• Provides PCS and MAC layer
functionality for 10.3 Gbit/s 10 Gigabit
Ethernet LAN PHY datastream.
• Supports framing, scrambling/
descrambling and pointer processing
for the following:
•
STS-192c (STM-64-64c).
INTERFACES
• Provides SATURN® POS-PHY™
Level 4 16-bit LVDS System-side
Interface (clocked at 700 MHz
nominal).
• Directly connects to optics via 16 bit by
622 MHz OIF SFI-4 (OIF99.102) or 16
bit by 622/645 MHz IEEE P802.3ae
XSBI line-side interfaces.
10 GIGABIT ETHERNET MAC
• Verifies frame integrity (FCS and
length checks).
BLOCK DIAGRAM
Rx SONET
BER
Monitor
LVDS I/F
APS
RXDATA+/-
RXCLK+/-
XSBI/
SFI-4
Rx
Interface
Rx
Transport
O/H
Processor
IAPS+/-
RPOH
RTOH
Rx Path
O/H
Processor
Rx Payload
Aligner
Rx 64B/
66B
Decoder
10 Gigabit
Ethernet
MAC
RSTAT
RSCLK
Ingress POS-PHY
Flexible Level 4
FIFO
Interface
Rx Cell/
Frame
Processor
RCTL+/-
RDAT+/-
RDCLK +/-
PL4 REF +/-
TXCLK+/-
TXDATA +/-
TXCLK_SRC+/-
XSBI/
SFI-4
Tx
Interface
Tx
Transport
O/H
Processor
Tx High-
Order Path
O/H
Processor
Tx 64B/66B
Encoder
10 Gigabit
Ethernet
MAC
TDCLK +/-
TDAT+/-
TCTL+/-
Egress POS-PHY
Flexible Level 4
FIFO
Interface
TSTAT
TSCLK
Tx Cell/
Frame
Processor
APS
LVDS I/F
Microprocessor
JTAG
TPOH
D[15:0]
A[14:0]
ALE
CSB
RDB
WRB
RSTB
INTB
OAPS+/-
PMC-2000181 (A2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
TDO
TDI
TMS
TCK
TRSTB
TTOH
Copyright PMC-Sierra, Inc. 2001
PMC [ PMC-SIERRA, INC ]
