PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
To eliminate conflicts for this access sequence, a recovery cycle is inserted between the micropro-
cessor access and any subsequent access. /PROC_ACK is driven until /PROC_CS is deactivated.
/SP_DATA_EN is driven until either /PROC_CS or /PROC_OE are deactivated.
Cycles (1) and (2) are grouped together in Figure 72 for the sake of convenience. These are nor-
mally two separate clock cycles.
NOTE: The timing characteristics (indicated by asterisks in the table following Figure 72)
are based on external component requirements.
1, 2
3
4
5
6
Tzsu
SYS_CLK
PROC_ADD
PROC_DATA
/PROC_CS(i)
/PROC_RD(i)i)
Tasu17
ADDR17(i)
/PROC_ACK(o)
/SP_DATA_EN(o)
Taa
Tcea
Tded
Tded
Taed
Tcaen
/SP_ADD_EN(o)
SP_DATA_DIR(o)
Tq
Tah
Tdsu
Tq
SP_DATA_CLK(o)
MEM_ADDR(i)
MEM_DATA(IO)
/MEM_CS(o)
Tasu
Tdh
Tq
Tq
Tzen
Tqmoe
/MEM_OE(o)
/MEM_WE(o)
NON_PROC WR CYCLE
PROC RD CYCLE
RECOVERY CYCLE NON-PROC CYCLE
Figure 72. Microprocessor RAM Read Cycle Timing
Parameter Signals
Symbol
Min
Max
Unit
Taa
(Refer to
Acknowledge assertion after
/PROC_CS or /PROC_RD;
/PROC_ACK
5
29
SYS_CLK
periods
NOTE below) whichever comes last
Tzen Time from z state to enable
MEM_DATA, /MEM_OE
1**
ns
ꢀꢉꢈ
PMC [ PMC-SIERRA, INC ]
