RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
FIGURE 81 RECEIVE DATA STRUCTURES ............................................... 155
FIGURE 83 NORMAL MODE REGISTERS MEMORY MAP ........................ 156
FIGURE 85 INTERRUPT HIERARCHY........................................................ 157
FIGURE 87 ADDQ_FIFO WORD STRUCTURE........................................... 159
FIGURE 89 LINE INTERFACE BLOCK ARCHITECTURE ........................... 164
FIGURE 91 CAPTURE OF T1 SIGNALING BITS......................................... 167
FIGURE 93 CAPTURE OF E1 SIGNALING BITS ........................................ 167
FIGURE 95 OUTPUT OF T1 SIGNALING BITS ........................................... 168
FIGURE 97 OUTPUT OF E1 SIGNALING BITS........................................... 169
FIGURE 99 SDF-MF FORMAT OF THE T_SIGNALING BUFFER ............... 186
FIGURE 100 R_CRC_SYNDROME MASK BIT TABLE LEGEND................ 207
FIGURE 101 BOUNDARY SCAN ARCHITECTURE..................................... 298
FIGURE 102 TAP CONTROLLER FINITE STATE MACHINE ...................... 300
FIGURE 103 INPUT OBSERVATION CELL (IN_CELL)................................ 303
FIGURE 104 OUTPUT CELL (OUT_CELL).................................................. 304
FIGURE 105 BIDIRECTIONAL CELL (IO_CELL) ......................................... 304
FIGURE 106 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS
305
FIGURE 107 PIPELINED SINGLE-CYCLE DESELECT SSRAM................. 306
FIGURE 108 PIPELINED ZBT SSRAM ........................................................ 306
FIGURE 109 SRC_INTF START OF TRANSFER TIMING (UTOPIA 1 ATM
MODE)
307
FIGURE 111 SRC_INTF END-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE)308
FIGURE 113 UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA 1 PHY
MODE)
308
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
xiii
PMC [ PMC-SIERRA, INC ]
