PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
The single write buffer represents a 2-cell pipeline, allowing the microprocessor
to fill one payload while the other one is waiting to be queued. A Not Full status
bit is provided, indicating whether the write buffer is capable of accepting at least
one cell.
Cell enqueuing is initiated by writing to the 14th word of the receive buffer. The
SAR assist receive cell transfer format is shown in Figure 11.
Figure 11
- SAR Assist Receive Cell Transfer Format
Register
Bits 31-24
Bits 23-16
Bits 15-8
Bits 7-0
SarRxLWord0
SarRxLWord1
SarRxLWord2
CRC Control
SarRxICI
H0
H1
H2
H3
Payload1
Payload2
Payload3
Payload4
•
•
•
•
•
•
•
•
•
•
•
•
SarRxLWord13
Payload45
Payload46
Payload47
Payload 48
Once there are 2 cells in the process of being en-queued, any further attempts to
write to the write buffer will be held pending until the first cell has been en-
queued.
The CRC Control gives each cell the option of being overwritten with an AAL5
CRC-32 or an OAM CRC-10 trailer. These CRC values cannot be invoked if
OAM cells are interspersed within AAL5 packets.
For frame traffic, it is necessary to write SarRxLWord0&1 for the first two cells,
SarRxLWord0 for the third cell and SarRxLWord0 for the last cell of the frame
SarRxLWord0&1 write of the first cell is required to reset the CRC, and establish
the ICI and header for the first pipe. SarRxLWord0&1 write of the second cell is
required to set the CRC for normal operation, and establish the ICI and header
for the second pipe. SarRxLWord0 write of the third cell is required to remove the
reset of the CRC established in the first cell and set the CRC for normal
operation. SarRxLWord0 write of the last cell is required to concatenate the CRC
onto the end of the cell. The middle cells of the frame only require the payload
to be updated.
10.9 Queue Engine
The queue engine performs the following functions:
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65
PMC [ PMC-SIERRA, INC ]
